Negative Capacitance Field Effect Research Articles

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Dielectrically modulated (DM) negative capacitance field effect transistor (NCFET)-based label-free biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nanocavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-side spacer region as a nanocavity, in a fully depleted silicon-on-insulator-based NCFET architecture. The ferroelectric (FE) layer in the metal-ferroelectric-insulator-semiconductor configuration meaningfully alters the impact of the drain’s electric field on the source-side electrostatics, which results in higher sensitivity. Having quantified the sensitivity of an FE-dielectric (FE-DE) gate-stack-based NCFET biosensor, we now propose to include a paraelectric (PE) layer between the FE and DE materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both stacks; here, a remarkable improvement is seen in the FE-PE-DE gate-stack-based NCFET, with nearly identical linearity performance, as seen from the high Pearson’s coefficient value ( r2⩾ 0.9). Therefore, to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), DE constant ( kBio ) values in the range of kBio = 4.5 to kBio = 75.99 are considered. Finally, the effect of scaling the channel length ( Lg ) on the sensitivity of the FE-PE-DE NCFET device is shown, and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET biosensor.

Gradient voltage amplification effect in FDSOI NCFET with thickness-variable ferroelectric layer

In this paper, a negative capacitance field effect transistor with thickness variable ferroelectric layer (TVFL NCFET) based on the fully depleted silicon on insulator (FDSOI) is proposed. The TVFL NCFET features the linearly increased ferroelectric layer thickness along the channel from source to drain. The gradient voltage amplification effect caused by the TVFL is analyzed according to the proposed capacitance model and simulation. Both of the model and numerical results indicate that the TVFL leads to a gradient increased electrostatic potential distribution along the bottom of the ferroelectric layer. The influences of gradient voltage amplification effect on the transfer characteristics, the output characteristic, the ratio between on-state-current (I ON) and off-state-current (I OFF), the drain induced barrier lowering (DIBL) and the subthreshold swing (SS) are investigated. The results show that the TVFL NCFET achieves the SS of 53.14 mV/dec, which is reduced by 19% when compared to the conventional NCFET. Meanwhile, large ION/IOFF is also realized and up to 1012 at most.

Strain tuning on Van der Waals negative capacitance transistors

Negative differential capacitance induced by the energy barrier formed by the nonlinear ferroelectric insulating layer during the phase transition in negative capacitance field effect transistors (NCFETs) can break through the fundamental thermionic limit of the metal-oxide-semiconductor field effect transistors (MOSFETs), which is set at a subthreshold swing (SS) of 60 mV/dec at room temperature for low-power switching. Strain engineering has been shown effective for modulating both intrinsic and coupled properties of ferroelectric materials. However, while the modulation of negative capacitance (NC) by strain primarily remains within theoretical predictions, there is a lack of experimental studies to explore its effect on NCFETs. This study introduces strain to NCFETs by utilizing the magnetostriction of Terfenol-D upon the applied magnetic field. Results reveal a decrease in SSmin from 43.5 mV/dec to 15.2 mV/dec with a compressive strain increase from 0 to −0.005%. Additionally, theoretical results by using time-evolving Ginzburg-Landau equations and Kirchhoff's laws demonstrate that compressive strain enhances both the amplitude and duration of transient NC in CuInP2S6, while vice versa under tensile strain. This work offers valuable insights for the design of NCFET devices.

TMD material investigation for a low hysteresis vdW NCFET logic transistor

Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP2S6 at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS2 with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS2 vdW NCFET has a high transconductance of 2.36 µS µm−1. A steep slope of 28.54 mV dec−1 is seen in MoS2 vdW NCFET which promises the performance of logic applications at a reduced supply voltage.

Negative Capacitance Field Effect Transistors based on Van der Waals 2D Materials.

Steep subthreshold swing (SS) is a decisive index for low energy consumption devices. However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann Tyranny, which limits the scaling of SS to sub-60mVdec-1 at room temperature. Ferroelectric gate stack with negative capacitance (NC) is proved to reduce the SS effectively by the amplification of the gate voltage. With the application of 2D ferroelectric materials, the NC FETs can be further improved in performance and downscaled to a smaller dimension as well. This review introduces some related concepts for in-depth understanding of NC FETs, including the NC, internal gate voltage, SS, negative drain-induced barrier lowering, negative differential resistance, single-domain state,and multi-domain state. Meanwhile, this work summarizes the recent advances of the 2D NC FETs. Moreover, the electrical characteristics of some high-performance NC FETs are expressed as well. The factors which affect the performance of the 2D NC FETs are also presented in this paper. Finally, this work gives a brief summary and outlook for the 2D NC FETs.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance

Achieving sub-60 mV/decade subthreshold swing in short channel Negative Capacitance Field Effect Transistor (NCFET) devices requires the utilization of a thicker Ferroelectric (FE) layer, where due to an interplay between the thickness and polarization gradient of the FE material, undesired effects such as Hysteresis and Negative Differential Resistance (NDR) may be seen in the device characteristics, which limits the expected improvement in the performance. In this work, with a Fully Depleted Silicon-on-insulator (FDSOI) baseline architecture, at a channel length of 14 nm, through utilizing a drain-sided Paraelectric (PE) spacer along with reduced drain doping while laterally splitting the gate stack into two halves such that the nature of the material on the source-sided and drain-sided stack is Ferroelectric and Paraelectric respectively, we show an NDR-free output characteristic. This also enables the incorporation of a thicker FE layer, without observing Hysteresis in the transfer characteristics, while ensuring significantly high Gain (gm/gds) along with sub-60 mV/decade subthreshold swing, at lower supply voltages.

DFT based atomic modeling and Analog/RF analysis of ferroelectric HfO2 based improved FET device

In this study, we systematically investigated the Analog/RF and linearity parameter of SM DGNCFET (single metal double gate negative capacitance field effect transistor) and DM DGNCFET (double metal double gate negative capacitance Field effect transistor) with the help of Cogenda Visual TCAD simulator, and also demonstrated the enhancement in the electronic and optical properties of Si-doping bulk structure by using the Quantum ATK. The analog parameters are enhanced for SM DGNCFET such better performance of switching ratio 279 times better, DIBL 54% lower, SS decay, and some other improved parameter transconductance, TGF and Radio frequency parameter is also enhanced, transconductance frequency product (TFP) for improving reliability and stability of device. Linearity parameters like that second and third order transconductance (gm2, g m3), voltage intercept point for 2nd, 3rd. Tran Blaha modified Becke Johnson (TB-mBJ) approxiamation gives the accurate band gap of crystal. In DFT based atomic study, 12.5% of Si doping in bulk structure reveals better results for ferroelectric HfO2 based crystal in the direct band gap of bandstructure is zero, Density of state (DOS) is also improved conductivity for Si doping crystal. Hence, Si doping in crystal structure is also better for conductivity.

Optimization of Subthreshold Swing and Hysteresis in Hf0.5Zr0.5O2-Based MoS2 Negative Capacitance Field-Effect Transistors by Modulating Capacitance Matching.

Negative capacitance field effect transistors made of Hf0.5Zr0.5O2 (HZO) are one of the most promising candidates for low-power-density devices because of the extremely steep subthreshold swing and high open-state currents resulting from the addition of ferroelectric materials in the gate dielectric layer. In this paper, HZO thin films were prepared by magnetron sputtering combined with rapid thermal annealing. Their ferroelectric properties were adjusted by changing the annealing temperature and the thickness of HZO. Two-dimensional MoS2 back-gate negative capacitance field-effect transistors (NCFETs) based on HZO were prepared as well. Different annealing temperatures, thicknesses of HZO thin films, and Al2O3 thicknesses were studied to achieve optimal capacitance matching, aiming to reduce both the subthreshold swing of the transistor and the hysteresis of the NCFET. The NCFET exhibits a minimum subthreshold swing as low as 27.9 mV/decade, negligible hysteresis (∼20 mV), and the ION/IOFF of up to 1.58 × 107. Moreover, a negative drain-induced barrier lowering effect and a negative differential resistance effect have been observed. This steep-slope transistor is compatible with standard CMOS manufacturing processes and attractive for 2D logic and sensor applications as well as future energy-efficient nanoelectronic devices with scaled power supplies.

Comparative study of Negative Capacitance Field Effect Transistors with different doped hafnium oxides

Negative Capacitance Field Effect Transistors are well known for their superior performance over MOSFET and are a viable candidate to succeed the baseline FET in time ahead. We have studied the performance of 32 nm planar MOSFET with doped hafnium dioxide as a ferroelectric material. The functioning of the NCFET is entirely dependent on the equivalence between the ferroelectric and MOS capacitance. Our simulation results clearly indicated that the Sr doped HfO2 has close capacitance matching with MOS capacitance, when compared with other dopant material (Si, Al and Zr). This also reflects in the performance parameters (drain current and transconductance characteristics) of the device designed. Also, we have designed a resistive load inverter with doped hafnium dioxide, Sr doped among them has an edge over the other ferroelectric material in terms of noise margin and static power dissipation.

Modeling of Ionizing Radiation Effects for Negative Capacitance Field-Effect Transistors

A theoretical model for simulating ionizing radiation effects on negative capacitance field-effect transistors (NCFETs) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure was established. Based on the model, the effects of total ionizing dose (TID) and dose rate on the surface potential, ferroelectric capacitance, voltage amplification factor, and transfer characteristics of NCFETs were investigated. The simulation results demonstrated that, with the increase in total dose, the curves of surface potential versus gate voltage and driving current versus gate voltage shift left significantly, resulting in the point of voltage amplification shifting left. Meanwhile, with the increase in dose rate, the amplitude of both the surface potential and driving current decreases slightly. Meanwhile, the derived result indicated that relatively thin ferroelectric thickness can effectively reduce the effect of TID. It is expected that this model can be helpful for analyzing the radiation effects of NCFETs.

Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance

Negative Capacitance Field Effect Transistors (NCFETs) offer the possibility of enhancing channel length scalability, with a key challenge being to ensure hysteresis and Negative Differential Resistance (NDR) free behavior. In this context, through TCAD-based simulations, for a symmetric Double-gate Silicon-on-Insulator (DG-SOI) baseline architecture with a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) configuration, we first examine the root cause of NDR as being the FE layer with a small number of strongly coupled domains, which allows the drain to lower the surface potential (ΨSs) and internal gate voltage (Vint) on the source side. With this understanding of NDR, the inclusion of a paraelectric (PE) layer on the drain side of the gate stack, by splitting the stack into two halves laterally, while keeping the thickness of the stack unchanged, minimizes the drain’s influence on the source-sided electrostatics. This results in the mitigation of NDR effects along with superior analog performance parameters, thus making these FE–PE gate stack-based NCFET devices suitable for analog circuit applications.

The Potential of ferroelectric HfO2 for Next-Generation Memory Device: Ferroelectric Properties and Applications

The discovery of the ferroelectricity of HfO<sub>2</sub> in 2011 has opened up new avenues for the application of ferroelectric technology. With the stability of ferroelectricity in a few nm scales, HfO<sub>2</sub> has become a valuable material for the development of next-generation electronic memory devices. The unique structure of HfO<sub>2</sub> gives rise to various ferroelectric properties and behaviors that can be utilized in different types of devices such as ferroelectric field effect transistors (FeFETs), negative capacitance field effect transistors (NCFETs), ferroelectric tunnel junctions (FTJs), and ferroelectric capacitors (FeCAPs). In this review, we explore the potential of HfO<sub>2</sub> for the high-density storage of data and low-energy consumption in next-generation devices. We demonstrate the operating principles and strengths of HfO<sub>2</sub> in various device applications, shedding light on how this material can help address the electronics industry's current challenges.

Impact of temperature on a ferroelectric interfaced negative capacitance double gate junctionless accumulation mode field effect transistor-compact model

Ferroelectric interfaced negative capacitance field effect transistors are gaining popularity for low power applications; however, as temperature is a constant influencing factor, further study is required to comprehend how these devices are influenced. Through a proposed compact model, this paper analytically investigates the influence of temperature on a ferroelectric interfaced negative capacitance double gate junctionless accumulation mode field effect transistor. This device integrates the benefits of negative capacitance with the junctionless accumulation mode structure. An extensive comparison of the proposed device is made with the existing structure to evaluate the benefits offered by the ferroelectric layer at different temperatures. The Landau–Khalatnikov equation and Pao–Sah integral are employed to obtain the surface potential and drain current model with temperature variation. Various key parameters of the device have been analysed extensively by varying the temperature from 200 to 500 K. It has been found that internal voltage amplification declines as temperature rises, but the sub-threshold swing increases from 46 to 72 mV decade −1 with an increase in temperature. Additionally, with a progressive rise in temperature, the loss of gain and degradation of gate capacitance are observed.

Investigation on the Negative Capacitance Field Effect Transistor with Dual Ferroelectric Region

This paper proposes a new structure of the negative capacitance field effect transistor (NCFET), which features of the dual ferroelectric region (DFR) when compared to the conventional NCFET. The dual ferroelectric region with FE1 region and FE2 region forms a non-uniform voltage amplification effect, leads to the significantly improvement of the gate control ability and modulates the electric characteristics of the NCFET. The mechanism of the voltage amplification effect, polarization reversal, channel surface electric field, and ferroelectric polarization intensity distributions are investigated. The influences of the ferroelectric parameters α and β on the electric characteristics are discussed. The results show that the DFR-NCFET is able to obtain a subthreshold swing (SS) below the Boltzmann limit (60 mV/dec) by increasing the ferroelectric parameter α of the FE2 region.

FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs

Given the short-channel effect immunity of junction-less architectures, further improvement in device performance can be obtained by using a Negative Capacitance based gate stack over such baseline devices. By benchmarking the baseline device, which is a partially Junction-less MOSFET structure, essentially a combination of the Junction-less and Bulk MOSFET device architectures, with experimental data, we then investigate the relative effect of the inclusion of a Ferroelectric (FE) material and Ferroelectric-Paraelectric (FE-PE) stack, respectively, on the existing dielectric (DE) gate stack of the baseline device, resembling a more practical Metal-Ferroelectric-Insulator-Semiconductor (MFIS) NCFET (Negative Capacitance Field Effect Transistor) structure. By ensuring Hysteresis-free transfer characteristics, positive output conductance and Sub-threshold Slope/Threshold Voltage invariability to drain voltage, the FE layer thickness and power supply voltage (maximum drain–source voltage) of the FE-DE and FE-PE-DE gate stacks are determined, which are nearly equivalent capacitively and therefore show similar digital device performance, with the FE-PE-DE gate stack based NCFET showing significantly better analog device performance.

Effect of shifted gate stack engineering over negative capacitance tunnel field effect transistor (NCTFET)

In this work, the performance of negative capacitance field effect transistor is closely investigated with different source material to improvise the transfer characteristics and sub-threshold swing. Tunnel Field Effect Transistor (TFET) being a strong competitor of conventional MOSFET for low power applications has its abilities to pull down Subthreshold Swing (SS) below fundamental limit but it has its own limitations of lower ION current and existence of ambipolar region for lower VGS voltage range. This ambipolar behavior is strongly seen in case of silicon source NCTFET but when source material is replaced with Germanium, a heterojunction is formed at source channel junction, and because of that, improvised result is obtained in terms of steeper subthreshold slope and ION/IOFF ratio. This work compares the transfer characteristics obtained in case of Si-Source and Ge-Source Negative Capacitance Tunnel Field Effect Transistor (NCTFET). The results obtained indicates that heterojunction NCTFET gives a subthreshold swing of 56.6 mV dec−1 and enhances ION/IOFF ratio to 0.24 × 108 in magnitude.

Analysis and Modeling of Current Mismatch in Negative Capacitance Field-Effect Transistor

In this work, we analyze the impact of random dopant fluctuations (RDFs) on the mismatch behavior of the negative capacitance field-effect transistor (NCFET). We observe that the drain current mismatch decreases in the NCFET compared to conventional MOSFET, and it further decreases with an increase in the thickness of the ferroelectric layer ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text {fe}}$ </tex-math></inline-formula> ). Metal–ferroelectric–metal–insulator–semiconductor (MFMIS)-type NCFET shows 24% and 22% improvement in mismatch power in comparison to baseline FET at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\vert {V}_{\text {GS}}\vert = {0.2}$ </tex-math></inline-formula> and 1 V, respectively. We show that the mismatch in NCFET is directly proportional to channel doping concentration, similar to baseline MOSFET. For the first time, we demonstrate that mismatch power varies nonmonotonically with the variation in the Landau coefficient <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> , and the other Landau coefficient <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> has an impact on mismatch at higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text {fe}}$ </tex-math></inline-formula> only. We also present a compact model, under the industry standard Berkeley Short-channel IGFET Model for Bulk MOSFET (BSIM-BULK) MOS model’s framework, which can accurately capture drain current mismatch from subthreshold to strong inversion region for NCFET. The model is extensively validated with the experimentally calibrated technology computer-aided design (TCAD) simulations across different biases and temperatures.

Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic design

The present reports an analytical modelling framework to provide insights into subthreshold logic design using metal-ferroelectric-metal–insulator-semiconductor (MFMIS) negative capacitance field effect transistor (NCFET). It is shown that the proposed model is effective in predicting supply voltage (V DD) dependent hysteresis as well as hysteresis-free voltage transfer characteristics (VTC) through the analytically obtained positive (hysteresis-free) and negative (hysteresis) values of gain (−dV O/dV IN) in NCFET based subthreshold inverter. The proposed subthreshold drain current model for NCFET has been extended to obtain closed-form analytical expressions of figures of merit of a subthreshold inverter such as nominal high and low output voltages, threshold logic voltage, and DC gain. The model while successfully capturing characteristics of MFMIS NCFETs is able to predict the occurrence of hysteresis in VTC due to negative differential resistance in the output characteristics of NCFET. Results show that an optimally designed MFMIS NCFET based inverter can achieve similar values of DC gain as exhibited by conventional MOSFET at ∼×(3–6) times lower supply voltages (V DD) along with an improvement in static and dynamic power dissipation. Results showcase an analytical modelling framework and its implications for reducing V DD for ultralow power subthreshold logic design with NCFETs.

Effect of back gate biasing in negative capacitance field effect transistor

In this paper, we have studied the effect of back gate bias technique in negative capacitance field effect transistor. In N-NCFET, OFF current decreases and threshold voltage increases with positive back gate bias, while with negative back gate bias, OFF current increases and threshold voltage decreases. This behavior of back gate bias in N-NCFET is quite different as compared to N-MOSFET. The primary reason behind this contradictory behavior is the dependence of internal node voltage (VMOS) on the body terminal of N-NCFET via bulk coupling factor. Further, we have utilized this property to design NCFET based inverter.Various figure of merits like noise margin, delay, static power dissipation and dynamic power dissipation is studied for the designed inverter. The designed inverter with suggested back gate bias shows 16% and 13.9% improved noise margin, and reduced delay performance respectively as compared to conventional NCFET without bias. Also, the power dissipation parameter (static and dynamic) is reduced by 90.1% and 3.8% respectively. We have also seen the effect of channel length scaling in the NCFET, decrement in the channel length improves the gate stack capacitance of NCFET which leads to decrement in OFF current at lower technology node.