Negative Capacitance Field-effect Transistors Research Articles

Fully Printed Negative-Capacitance Field-Effect Transistors with Ultralow Subthreshold Swing and High Inverter Signal Gain.

The switching of conventional field-effect transistors (FETs) is limited by the Boltzmann barrier of thermionic emission, which prevents the realization of low-power electronics. In order to overcome this limitation, among others, unconventional device geometry with a ferroelectric/dielectric insulator stack has been proposed to demonstrate stable negative-capacitance behavior. Here, the switching of the ferroelectric layer behaves like a step-up amplifier and results in a body factor less than 1. This implies a larger change in the semiconductor surface potential compared to the applied gate voltage variation. The transistors with such ferroelectric/dielectric stack are known as negative-capacitance field-effect transistors (nc-FETs), and can demonstrate a subthreshold slope lower than the Boltzmann's limit (60 mV/decade). While nc-FETs have typically been realized with high-vacuum-deposition processes, here we show fully printed nc-FETs with amorphous indium-gallium-zinc oxide (a-IGZO) as the semiconductor material, Al2O3 as the dielectric, and poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as the polymer ferroelectric. The printed nc-FETs demonstrate an extremely low subthreshold slope of ∼2.3 mV/decade at room temperature, which remains below the Boltzmann's limit for over 5 orders of magnitude of drain currents. Furthermore, the unipolar depletion-load-type inverters fabricated using n-type nc-FETs have demonstrated an extraordinary signal gain of 2691.

Steep Slope Field Effect Transistors Based on 2D Materials

AbstractWith field effect transistor (FET) sustained to downscale to sub‐10 nm nodes, performance degradation originates from short channel effects (SCEs) degradation and power consumption increment attributed to inhibition of supply voltage (VDD) scaling down proportionally caused by thermionic limit subthreshold swing (SS) (60 mV dec−1) pose substantial challenges for today's semiconductor industry. To further sustain the Moore's law life, incorporation of new device concepts or new materials are imperative. 2D materials are predicted to be able to combat SCEs by virtue of high carrier mobility maintainability regardless of thickness thinning down, dangling bonds free surface and atomic thickness, which contributes to super gate electrostatic controllability. To overcome increasing power dissipation problem, new device structures including negative capacitance FET (NCFET), tunnel FET (TFET), dirac source FET (DSFET) and the like, which show superiority in decreasing VDD by lowering SS below thermionic limit of 60 mV dec−1 have been brought out. The combination of 2D materials and ultralow steep slope device structures holds great promise for low power‐dissipation electronics, which encompass both suppressed SCEs and reduced VDD simultaneously, leading to improved device performance and lowered power dissipation.

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Dielectrically modulated (DM) negative capacitance field effect transistor (NCFET)-based label-free biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nanocavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-side spacer region as a nanocavity, in a fully depleted silicon-on-insulator-based NCFET architecture. The ferroelectric (FE) layer in the metal-ferroelectric-insulator-semiconductor configuration meaningfully alters the impact of the drain’s electric field on the source-side electrostatics, which results in higher sensitivity. Having quantified the sensitivity of an FE-dielectric (FE-DE) gate-stack-based NCFET biosensor, we now propose to include a paraelectric (PE) layer between the FE and DE materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both stacks; here, a remarkable improvement is seen in the FE-PE-DE gate-stack-based NCFET, with nearly identical linearity performance, as seen from the high Pearson’s coefficient value ( r2⩾ 0.9). Therefore, to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), DE constant ( kBio ) values in the range of kBio = 4.5 to kBio = 75.99 are considered. Finally, the effect of scaling the channel length ( Lg ) on the sensitivity of the FE-PE-DE NCFET device is shown, and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET biosensor.

Gradient voltage amplification effect in FDSOI NCFET with thickness-variable ferroelectric layer

In this paper, a negative capacitance field effect transistor with thickness variable ferroelectric layer (TVFL NCFET) based on the fully depleted silicon on insulator (FDSOI) is proposed. The TVFL NCFET features the linearly increased ferroelectric layer thickness along the channel from source to drain. The gradient voltage amplification effect caused by the TVFL is analyzed according to the proposed capacitance model and simulation. Both of the model and numerical results indicate that the TVFL leads to a gradient increased electrostatic potential distribution along the bottom of the ferroelectric layer. The influences of gradient voltage amplification effect on the transfer characteristics, the output characteristic, the ratio between on-state-current (I ON) and off-state-current (I OFF), the drain induced barrier lowering (DIBL) and the subthreshold swing (SS) are investigated. The results show that the TVFL NCFET achieves the SS of 53.14 mV/dec, which is reduced by 19% when compared to the conventional NCFET. Meanwhile, large ION/IOFF is also realized and up to 1012 at most.

Strain tuning on Van der Waals negative capacitance transistors

Negative differential capacitance induced by the energy barrier formed by the nonlinear ferroelectric insulating layer during the phase transition in negative capacitance field effect transistors (NCFETs) can break through the fundamental thermionic limit of the metal-oxide-semiconductor field effect transistors (MOSFETs), which is set at a subthreshold swing (SS) of 60 mV/dec at room temperature for low-power switching. Strain engineering has been shown effective for modulating both intrinsic and coupled properties of ferroelectric materials. However, while the modulation of negative capacitance (NC) by strain primarily remains within theoretical predictions, there is a lack of experimental studies to explore its effect on NCFETs. This study introduces strain to NCFETs by utilizing the magnetostriction of Terfenol-D upon the applied magnetic field. Results reveal a decrease in SSmin from 43.5 mV/dec to 15.2 mV/dec with a compressive strain increase from 0 to −0.005%. Additionally, theoretical results by using time-evolving Ginzburg-Landau equations and Kirchhoff's laws demonstrate that compressive strain enhances both the amplitude and duration of transient NC in CuInP2S6, while vice versa under tensile strain. This work offers valuable insights for the design of NCFET devices.

Analysis and Mitigation of Negative Differential Resistance Effects with Hetero-gate Dielectric Layer in Negative-capacitance Field-effect Transistors

Analysis and Mitigation of Negative Differential Resistance Effects with Hetero-gate Dielectric Layer in Negative-capacitance Field-effect Transistors

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (fOSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of fOSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.

TMD material investigation for a low hysteresis vdW NCFET logic transistor

Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP2S6 at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS2 with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS2 vdW NCFET has a high transconductance of 2.36 µS µm−1. A steep slope of 28.54 mV dec−1 is seen in MoS2 vdW NCFET which promises the performance of logic applications at a reduced supply voltage.

Complementary negative capacitance field-effect transistors based on vertically stacked van der Waals heterostructures

Complementary field-effect transistors (CFETs) with a vertically stacked n-FET/p-FET configuration can provide a promising solution to boost area efficiency. However, the substantial power dissipation exhibited by these CFET devices poses a notable challenge to the energy efficiency. By combining a negative-capacitance field-effect transistor (NCFET) and a CFET, the problem of excessive power consumption can be solved. By using a negative-capacitance gate stack, the supply voltage (Vdd) applied to the gate of the CFET is increased, resulting in a reduction in power consumption. Here, we experimentally demonstrate a vertically integrated complementary negative capacitance field-effect transistor (NC-CFET) that combines tungsten diselenide (WSe2) p-NCFET and molybdenum disulfide (MoS2) n-NCFET. With the hexagonal boron nitride/copper indium thiophosphate CuInP2S6 (CIPS) dielectric stack, both n-type and p-type van der Waals (vdW) NCFETs exhibit sub-60 mV/decade switching characteristics. The vdW NC-CFET exhibits a voltage gain of 78.34 and a power consumption of 129.7 pW at a supply voltage of 1 V. These device characteristics demonstrate the great potential of the vdW NC-CFET for high density and low power applications.

DFT based atomic modeling and temperature analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET

In this report, Density Functional Theory (DFT) based calculation using a Quantum Atomistic Tool Kit (ATK) simulator is done for the hafnia-based ferroelectric material. The band structure, projected density of states (PDOS), and Hartree potential (VH) are taken into account for hafnium oxide (HfO2) and silicon-doped hafnium oxide (Si-doped HfO2). Further, we analyze the temperature variation impact on analog parameters and voltage transfer characteristic (VTC) curve of inverter application of Modified Negative Capacitance Field-Effect-Transistor (NCFET) using the Visual Technology-Computer-Aided-Design (TCAD) simulator. The Modified NCFET structure enhances the DC parameters like leakage current (IOFF) and Subthreshold Swing (SS) compared to the conventional NCFET structure. With the temperature impact, the variation in the parameters of Modified NCFET is discussed at 250 K, 275 K, 300 K, 325 K, and 350 K like transconductance (gm), output conductance (gd), early voltage (VEA) shows the increment as we move from 250 K to 350 K. The short channel effects (SCEs) like Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) decrease with the temperature fall at 32.98% and 34.74%, respectively. Further, the VTC curve, Noise Margin (NM), and propagation delay of Modified NCFET-based inverter are discussed with the impact of temperature. The propagation delay for the circuit decreased by 67.94% with the rise in the temperature. These factors show that the Modified NCFET-based inverter gives a fast switching performance at high temperatures.

Negative capacitance field-effect transistors based on ferroelectric AlScN and 2D MoS2

Al0.68Sc0.32N (AlScN) has gained attention for its outstanding ferroelectric properties, including a high coercive field and high remnant polarization. Although AlScN-based ferroelectric field-effect transistors (FETs) for memory applications have been demonstrated, a device for logic applications with minimal hysteresis has not been reported. This study reports on the transport characteristics of a MoS2 negative capacitance FET (NCFET) based on an AlScN ferroelectric material. We experimentally demonstrate the effect of a dielectric layer in the gate stack on the memory window and subthreshold swing (SS) of the NCFET. We show that the hysteresis behavior of transfer characteristics in the NCFET can be minimized with the inclusion of a non-ferroelectric dielectric layer, which fulfills the capacitance-matching condition. Remarkably, we also observe the NC effect in MoS2/AlScN NCFETs arrays based on large-area monolayer MoS2 synthesized by chemical vapor deposition, showing the SS values smaller than its thermionic limit (∼36 to 60 mV/dec) and minimal variation in threshold voltages (<20 mV).

Negative Capacitance Field Effect Transistors based on Van der Waals 2D Materials.

Steep subthreshold swing (SS) is a decisive index for low energy consumption devices. However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann Tyranny, which limits the scaling of SS to sub-60mVdec-1 at room temperature. Ferroelectric gate stack with negative capacitance (NC) is proved to reduce the SS effectively by the amplification of the gate voltage. With the application of 2D ferroelectric materials, the NC FETs can be further improved in performance and downscaled to a smaller dimension as well. This review introduces some related concepts for in-depth understanding of NC FETs, including the NC, internal gate voltage, SS, negative drain-induced barrier lowering, negative differential resistance, single-domain state,and multi-domain state. Meanwhile, this work summarizes the recent advances of the 2D NC FETs. Moreover, the electrical characteristics of some high-performance NC FETs are expressed as well. The factors which affect the performance of the 2D NC FETs are also presented in this paper. Finally, this work gives a brief summary and outlook for the 2D NC FETs.

Exploring the impact of domain numbers on negative capacitance effects in ferroelectric Device-Circuit Co-Design

This paper explores the performance of Hf0.5Zr0.5O2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond complementary metal–oxide–semiconductor (CMOS) technology. For the first time, we investigate the impact of ferroelectric (FE) domain numbers on the negative capacitance (NC) effect, energy dissipation, NC effect voltage window, polarization ramping rate, voltage amplification (ANC), and oscillation frequency of a 5-stage HZO-NCFET inverter-based ring oscillator (HZO-NCFET-RO). The results show that HZO-NCFET is suitable for low-voltage and high-speed applications, providing a significant increase in ANC concerning the conventional PZT-NCFET and P(VDF-TrFE)-NCFET. Our study suggests that the HZO intrinsic NC effect time scale is tiny and limited by the FE switching. We show that the switching time of HZO is ∼20 times faster than the traditional FE [Pb(Nb0.04Zr0.28Ti0.68)O3]. Finally, the proposed 5-stage HZO-NCFET-RO offers superior performance with a 26% higher oscillation frequency and a 94.42% reduction in power dissipation compared to standard 5-stage CMOS inverter-based RO. These findings highlight the potential of HZO-stacked NCFET as an alternative device for the future beyond-CMOS technology.

Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors.

Boltzmann distribution thermal tails of carriers restrain the subthreshold swing (SS) of field-effect transistors (FETs) to be lower than 60 mV/decade at room temperature, which restrains the reduction of operate-voltage and power consumption of transistors. The negative-capacitance FET (NC FET) is expected to break through this physical limit and obtain a steep SS by amplifying the gate voltage through the negative capacitance effect of the ferroelectric thin film, providing a new way to further reduce the power consumption of the transistor at the end of Moore's law. Here, we show a MoS2 NC FET with a CuInP2S6 ferroelectric, exhibiting a large on/off ratio of 108, a steep SS as low as 6 mV/decade, and a wide sub-60 mV/decade drain current range of more than 4 orders of magnitude while sacrificially inducing a huge hysteresis larger than 500 mV. Furthermore, we found that by inserting the h-phase boron nitride (h-BN) layer with suitable thickness, the dielectric capacitance matches the ferroelectric negative capacitance better, and thus the hysteresis on the transfer curve is reduced, and the ideal switching-behavior transistors with SS as low as 62 mV/decade and only 5 mV negligible hysteresis were obtained. Our work demonstrates that under the capacitance-matching condition, the hysteresis-free negative-capacitance transistors do not act as the predicted steep-slope transistors, but their voltage-saving still occurs instead as a type of effective transconductance booster with more than 20 times transconductance amplification.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Exploring the Physical Origin of the Negative Capacitance Effect in a Metal–Ferroelectric–Metal–Dielectric Structure

AbstractThe ferroelectric negative capacitance (NC) draws a great deal of attention for low‐power negative capacitance field‐effect transistors (NCFET) and NC capacitors. The fabrication of steep‐slope FET (subthreshold swing < 60mVdec−1) is reported, followed by modeling approaches. While the device fabrication favors a ferroelectric gate structure without interlayer metal, many NCFET models adopt interlayer metal between the ferroelectric layer and metal–insulator–semiconductor structure. The metal interlayer averages out spatial variation in the ferroelectric polarization, enabling a compact charge‐based relation between the layers. In addition, the approach assumes that the NC effect emerges from the ferroelectric layer regardless of the metal interlayer, which is not necessarily probable. This work reinvestigates the possible NC effect in ferroelectric–dielectric capacitors connected by a metal interlayer. The experiment confirms that the NC effect in the metal–ferroelectric–dielectric–metal structure does not appear in the metal–ferroelectric–metal–dielectric–metal structure. These results are inconsistent with the multidomain‐1D Landau–Ginzburg‐Devonshire model. In contrast, the suppression of the NC effect in the structure is fully explained by the advanced inhomogeneous stray‐field energy model, which simulates the dynamic evolution of polarization and screening charges. Therefore, an NCFET with a metal interlayer is impractical.

Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance

Achieving sub-60 mV/decade subthreshold swing in short channel Negative Capacitance Field Effect Transistor (NCFET) devices requires the utilization of a thicker Ferroelectric (FE) layer, where due to an interplay between the thickness and polarization gradient of the FE material, undesired effects such as Hysteresis and Negative Differential Resistance (NDR) may be seen in the device characteristics, which limits the expected improvement in the performance. In this work, with a Fully Depleted Silicon-on-insulator (FDSOI) baseline architecture, at a channel length of 14 nm, through utilizing a drain-sided Paraelectric (PE) spacer along with reduced drain doping while laterally splitting the gate stack into two halves such that the nature of the material on the source-sided and drain-sided stack is Ferroelectric and Paraelectric respectively, we show an NDR-free output characteristic. This also enables the incorporation of a thicker FE layer, without observing Hysteresis in the transfer characteristics, while ensuring significantly high Gain (gm/gds) along with sub-60 mV/decade subthreshold swing, at lower supply voltages.

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

In order to better understand the possible improvement through the incorporation of a ferroelectric (FE) layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal–FE–metal–insulator–semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting a sub-60 mV dec−1 subthreshold swing and a negative drain induced barrier lowering (DIBL), the results indicate that at lower FE thickness, the performance of the NC field effect transistor (NCFET) is primarily governed by the electrostatic integrity of the baseline transistor, i.e. the CYL architecture outperforms planar DG NCFET. However, for relatively thicker T FE, the performance of an MFMIS NCFET is strongly governed by the FE coupling, which indicates the comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving a sub-60 mV dec−1 subthreshold swing and DIBL-free characteristics in MFMIS NC transistors.

DFT based atomic modeling and Analog/RF analysis of ferroelectric HfO2 based improved FET device

In this study, we systematically investigated the Analog/RF and linearity parameter of SM DGNCFET (single metal double gate negative capacitance field effect transistor) and DM DGNCFET (double metal double gate negative capacitance Field effect transistor) with the help of Cogenda Visual TCAD simulator, and also demonstrated the enhancement in the electronic and optical properties of Si-doping bulk structure by using the Quantum ATK. The analog parameters are enhanced for SM DGNCFET such better performance of switching ratio 279 times better, DIBL 54% lower, SS decay, and some other improved parameter transconductance, TGF and Radio frequency parameter is also enhanced, transconductance frequency product (TFP) for improving reliability and stability of device. Linearity parameters like that second and third order transconductance (gm2, g m3), voltage intercept point for 2nd, 3rd. Tran Blaha modified Becke Johnson (TB-mBJ) approxiamation gives the accurate band gap of crystal. In DFT based atomic study, 12.5% of Si doping in bulk structure reveals better results for ferroelectric HfO2 based crystal in the direct band gap of bandstructure is zero, Density of state (DOS) is also improved conductivity for Si doping crystal. Hence, Si doping in crystal structure is also better for conductivity.

Optimization of Subthreshold Swing and Hysteresis in Hf0.5Zr0.5O2-Based MoS2 Negative Capacitance Field-Effect Transistors by Modulating Capacitance Matching.

Negative capacitance field effect transistors made of Hf0.5Zr0.5O2 (HZO) are one of the most promising candidates for low-power-density devices because of the extremely steep subthreshold swing and high open-state currents resulting from the addition of ferroelectric materials in the gate dielectric layer. In this paper, HZO thin films were prepared by magnetron sputtering combined with rapid thermal annealing. Their ferroelectric properties were adjusted by changing the annealing temperature and the thickness of HZO. Two-dimensional MoS2 back-gate negative capacitance field-effect transistors (NCFETs) based on HZO were prepared as well. Different annealing temperatures, thicknesses of HZO thin films, and Al2O3 thicknesses were studied to achieve optimal capacitance matching, aiming to reduce both the subthreshold swing of the transistor and the hysteresis of the NCFET. The NCFET exhibits a minimum subthreshold swing as low as 27.9 mV/decade, negligible hysteresis (∼20 mV), and the ION/IOFF of up to 1.58 × 107. Moreover, a negative drain-induced barrier lowering effect and a negative differential resistance effect have been observed. This steep-slope transistor is compatible with standard CMOS manufacturing processes and attractive for 2D logic and sensor applications as well as future energy-efficient nanoelectronic devices with scaled power supplies.