Negative Capacitance Behavior Research Articles

The impact of temperature and frequency on negative capacitance and dielectric attributes in NiCo2O4 bulk ceramic

This paper presents a complete analysis of the electrical and dielectric characteristics of NiCo2O4 (NCO) bulk ceramic synthesized by the co-precipitation process as a future electronic device material. The structural analysis following the synthesis process revealed the formation of cubic-phase spinel NCO in the shape of nanospheres, with an approximate diameter of 25 nm. The present study aimed to examine the relationship between capacitance and conductance for the NCO under investigation, focusing on their frequency and temperature dependencies. The frequency range of interest ranged from 100 Hz to 1.5 MHz, while the temperature range considered was from 300 K to 450 K. The C/f plot has exhibited the phenomenon of negative capacitance, which may be attributed to the augmentation of polarization and the incorporation of additional minority carriers inside the structure. The dielectric parameters, such as permittivity, dielectric loss, alternating current conductance, and electrical modulus, were determined by capacitance and conductance measurements, taking into account their frequency and temperature reliance. All dielectric calculations were influenced by negative capacitance measurements. The negative capacitance feature of NiCo2O4 is attributed to the ferroelectric properties of the Ni and Co elements in its composition. In conclusion, this paper has made a valuable contribution to the existing body of literature by enhancing our comprehension of the negative capacitance behavior and dielectric characteristics of the NCO.

An Informetric View to the Negative Capacitance Phenomenon at Interlayered Metal-Semiconductor Structures and Distinct Electronic Devices

Negative Capacitance (NC) phenomenon, which can be explained as the material exhibiting an inductive behavior, is often referred to as "anomalous" or "abnormal" in the literature. Especially in the forward bias/deposition region, the presence of surface states (Nss) and their relaxation times (τ), series resistance (Rs), minority carrier injection, interface charge loss in occupied states under the Fermi energy level, parasitic inductance, or poor measuring equipment calibration problems can be counted among the causes of this phenomenon. Studies on NC behavior have shown that this behavior can be observed for different frequencies, temperatures, and related parameters at forward biases. However, the NC behavior, which appears as an unidentified peak in admittance spectroscopy data, is not yet fully understood. Ultimately, this study aims to compile and analyze the NC reported in selected scientific studies, investigate the source of this phenomenon, and observe statistics in a general view.

Negative Capacitance and Intrinsic Ferroelectric Behavior in α-MoO3 Culminating as a Robust Piezoelectric Energy Harvester

Driven by the notion that the spectrum of ferroelectric applications can be widened and the current subset of materials could be replaced with earth-abundant, lead-free materials, single-phase α-MoO3 (MO) with biaxial van der Waals gap was synthesized, revealing an orthorhombic Pmcn symmetry with a layered ABAB... sequence, with mirrored A and B layers. The force-driven dielectric constant of MO was found to be 12.5 at 0.5 N force level, which showed dielectric saturation behavior with increasing dynamic force. Ferroelectric studies revealed a maximum of 46% efficiency at 10 kV/cm external electric field, and piezoelectric modulus (d33) of 30 pC/N was obtained using the Berlincourt method. Negative capacitance (NC) effects were observed and attributed to the ferroelectric-induced emf and the inductive reactance, in accordance with Lenz’s law. Based on the confluence of the aforementioned features, a piezoelectric energy harvester (PEH) was fabricated, which reached a peak voltage of 4 V under repetitive finger tapping. The power density of the PEH under 100 MΩ resistive load was found to be 7.32 × 10–1 μW/cm2. This enshrines MO as a promising piezoelectric candidate with exotic properties that can be tailored to have multifaceted applications in the realm of sensing and energy harvesting to drive Internet-of-Things and Industry 4.0.

The investigation of interlayer (CeO2:PVC) effects on the dielectric features of Au-Si (MS) Schottky barrier diodes (SBDs) using the impedance spectroscopy method

In this research, Au-PVC-Si (MPS1), Au-(CeO2: PVC)-Si (MPS2) Schottky barrier diodes (SBDs) have been grown on n-type silicon (n-Si) with the aim of investigating the frequency dependence and the effect of polymer interlayer on dielectric parameters such as complex dielectric constant (ε = ε′–iε″), ac-conductivity (σ ac), and complex electric-modulus (M = M′ + iM″). For this purpose, the mentioned parameters have been calculated by measuring C/G-f in wide-range frequency (100 Hz–1 MHz) at room temperature for all three diodes and how the effect of PVC and (CeO2: PVC) interlayer on dielectric parameters of Au-Si (MS) has been studied. In the low-frequency range, plot C-f shows a negative capacitance behavior (NC) that causes the dielectric constant to be negative in this frequency range. Such negative behavior can be described using capture and emissions of carriers at interface states. The results of examining the frequency dependence of dielectric parameters showed that these parameters are sensitive to the frequency, especially the low-frequency range, which is due to the surface polarization and interface states. Also, the conduction mechanism of samples was investigated through the slope of the lnσ ac- lnω plot. The σ ac value for all three diodes at low frequencies is almost independent of the frequency, which is related to dc conductivity (σ dc). The slope value of the lnσ ac- lnω plot in the high frequencies was smaller than the unit which can be described by the hopping mechanism. The presence of the PVC and (PVC: CeO2) interlayer in the metal-semiconductor junction has increased the dielectric constant and conductivity of MPS compared to MS-type SBDs.

Negative Capacitance Behavior at Low Frequencies of Nitrogen-Doped Polyethylenimine-Functionalized Graphene Quantum Dots-Based Structure

Negative Capacitance Behavior at Low Frequencies of Nitrogen-Doped Polyethylenimine-Functionalized Graphene Quantum Dots-Based Structure

The Opportunity of Negative Capacitance Behavior in Flash Memory for High‐Density and Energy‐Efficient In‐Memory Computing Applications

AbstractFlash memory is a promising candidate for use in in‐memory computing (IMC) owing to its multistate operations, high on/off ratio, non‐volatility, and the maturity of device technologies. However, its high operation voltage, slow operation speed, and string array structure severely degrade the energy efficiency of IMC. To address these challenges, a novel negative capacitance‐flash (NC‐flash) memory‐based IMC architecture is proposed. To stabilize and utilize the negative capacitance (NC) effect, a HfO2‐based reversible single‐domain ferroelectric (RSFE) layer is developed by coupling the flexoelectric and surface effects, which generates a large internal field and surface polarization pinning. Furthermore, NC‐flash memory is demonstrated for the first time by introducing a RSFE and dielectric heterostructure layer in which the NC effect is stabilized as a blocking layer. Consequently, an energy‐efficient and high‐throughput IMC is successfully demonstrated using an AND flash‐like cell arrangement and source‐follower/charge‐sharing vector‐matrix multiplication operation on a high‐performance NC‐flash memory.

Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack

With the superior analog/RF performance of planar device architectures such as fully depleted silicon-on-insulator (FDSOI) MOSFETs, it becomes important to investigate the impact of a ferroelectric material in the gate stack, resulting in negative capacitance (NC) behavior, on the device performance. In this work, through calibrating the FDSOI MOSFET (as the baseline device architecture) with experimental data, we compare the impact of ferroelectric–dielectric (FE–DE) and ferroelectric–paraelectric–dielectric (FE–PE–DE) gate stacks on the electrostatics of an NCFET device for a practically realisable metal–ferroelectric–insulator–semiconductor (MFIS) structure. A suitable thickness of the ferroelectric (FE) layer in the FE–DE stack and the maximum drain–source voltage () that can be applied (determining the power supply voltage), are identified so as to ensure that constraints such as no negative differential resistance (NDR) effects, threshold voltage (), sub-threshold slope (SS) invariability with drain voltage variations and hysteresis-free behavior in transfer characteristics (–) are all satisfied. From the thickness of the FE layer in the FE–DE stack, the thickness of the FE layer in the FE–PE–DE stack (PE layer thickness is fixed at 1 nm) is determined where with a thicker FE layer, we obtain similar capacitance from the FE–PE–DE gate stack to that obtained from the FE–DE stack, while meeting all the constraints applied to the FE–DE stack based NCFET, enabling determination of the power supply voltage. Through showing good SSs with reduced output conductance (), resulting in improved dc gain () and improved linearity parameters ( and ) along with scaling of power supply, an FE–PE–DE stack shows better analog performance, with lower power consumption, compared to an FE–DE stack, for an FDSOI NCFET, at 14 nm gate length.

Nonhysteretic Condition in Negative Capacitance Junctionless FETs

This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77K to 400K. This approach has been assessed with numerical TCAD simulations.

Negative Capacitance Dual Electrode Junctionless TFET Based on Si Doped HfO 2 Ferroelectric Layer: Proposal and Optimization

This work reports negative capacitance dual electrode junctionless tunnel field effect transistor (NC-DE-JLTFET) based on Si doped HfO 2 ferroelectric (FE) layer as gate-stack. This FE layer is sandwiched between conventional gate dielectric layer and gate metal electrode. As the domains of FE get aligned due to polarization in the applied electric field directions it realizes intrinsic voltage amplification. This facilitates the smaller voltage swing in the gate voltage resulting in a larger swing in drive current. This enhances gate controlability, improves scalability, lowers threshold voltage and steepers sub-threshold slope (SS). However the most crucial designing aspect of negative capacitance (NC) based device is stabilizing the net capacitance of the structure otherwise it can cause system instability due to the NC behavior. In order to stabilize this NC effect here optimization of FE layer thickness has been carried out by parametric sweep optimization. The study reported minimum SS as 20 mV/dec with FE thickness of 2.5 nm. As JLTFET is a dopingless structure, source and drain side dielectric oxide thicknesses dictate the source and drain side induced doping, respectively. Hence the device performance estimation in terms of these thickness variations is also presented here in detail.

Electron transport characteristics of FeGa, Ni/n-Si junctions by impedance spectroscopy

In this work, we have investigated electron transport across Galfenol (Fe x Ga 1-x ) and Nickel-based Schottky contacts deposited onto n-Si substrates using conventional DC current-voltage (I–V) measurements and have uniquely studied the effects of improper back contact causing additional bias dependent Resistance-capacitance (R–C) components using AC Impedance spectroscopy by choosing proper equivalent circuit models. Junction barrier height and ideality factor were obtained from DC current-voltage characteristics, and bias dependent impedance measurements have been carried out. From Impedance spectroscopy analysis the magnitudes of depletion layer capacitance and barrier height have been calculated and have been compared for both the junctions, and the effect of additional components has been distinguished. Negative capacitance behaviour at lower frequencies and higher forward bias regime has been observed, which might be attributed to interface states in presence of injected charge carriers and by choosing an equivalent circuit having inductor-resistor (R-L) type relaxation, better fit of experimental Nyquist plots of FeGa Schottky junction have been achieved. • FeGa and Nickel based Schottky Junctions have been deposited onto n-Si substrates using RF magnetron Sputtering. • Junction parameters have been calculated using conventional DC and, AC Impedance measurements. • Using equivalent circuit; bias dependency of both Schottky and Ohmic interfaces for has been studied.

Negative capacitance effects in ferroelectric heterostructures: A theoretical perspective

In a heterogeneous system, ferroelectric materials can exhibit negative capacitance (NC) behavior given that the overall capacitance of the system remains positive. Such NC effects may lead to differential amplification in local potential and can provide an enhanced charge and capacitance response for the whole system compared to their constituents. Such intriguing implications of NC phenomena have prompted the design and exploration of many ferroelectric-based electronic devices to not only achieve an improved performance but potentially also overcome some fundamental limits of standard transistors. However, the microscopic physical origin as well as the true nature of the NC effect, and direct experimental evidence remain elusive and debatable. To that end, in this article, we provide a comprehensive theoretical perspective on the current understanding of the underlying physical mechanism of the NC effect in the ferroelectric material. Based upon the fundamental physics of ferroelectric material, we discuss different assumptions, conditions, and distinct features of the quasi-static NC effect in the single-domain and multi-domain scenarios. While the quasi-static and hysteresis-free NC effect was initially propounded in the context of a single-domain scenario, we highlight that similar effects can be observed in multi-domain FEs with soft domain-wall (DW) displacement. Furthermore, to obtain the soft-DW, the gradient energy coefficient of the FE material is required to be higher as well as the ferroelectric thickness is required to be lower than some critical values. If those requirements are not met, then the DW becomes hard and their displacement would lead to hysteretic NC effects, which are adiabatically irreversible. In addition to the quasi-static NC, we discuss different mechanisms that can potentially lead to the transient NC effects. Furthermore, we discuss different existing experimental results by correlating their distinct features with different types of NC attributes and provide guidelines for new experiments that can potentially provide new insights on unveiling the real origin of NC phenomena.

Computational Investigation of Negative Capacitance Coaxially Gated Carbon Nanotube Field-Effect Transistors

In this article, we present a computational investigation on nanoscale coaxial-gate negativecapacitance carbon nanotube field-effect transistor (NC CNTFET). The proposed nanodevice is endowed with metal- ferroelectric-metal-insulator-semiconductor (MFMIS) structure. The simulation approach is based on solving self-consistently the nonequilibrium Green's function formalism with the NC FET electrostatics considering ballistic transport conditions. The computational assessment includes the switching performance and shortchannel effects (SCEs) in NC CNTFETs. The negative capacitance behavior of the ferroelectric has been found efficient in boosting the performance of nanoscaleCNTFETs in terms of subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON-current, current ratio, and intrinsic delay. In addition, we show the capability of MFMIS configuration in improving the current ratio and SS of CNTFETs with ultrascaled gate lengths. The role of the ferroelectric layer thickness in enhancing the NC CNTFET performance is also studied, where improved performance has been recorded using thicker ferroelectric layer. Achieving high ION/IOFF current ratio, sub-kT SS, and improved immunity against SCEs makes the NC CNTFET as a potential candidate for modern CNT-based nanoelectronics.

Temperature and voltage dependence C–V and G/ω–V characteristics in Au/n-type GaAs metal–semiconductor structures and the source of negative capacitance

To investigation the phenomena of negative capacitance, we examined the capacitance–voltage (C–V), conductance–voltage (G/ω–V), and series resistance–voltage (RS–V) properties of Au/n-type GaAs metal–semiconductor (MS) structure in the different temperatures (80–415 K) and + 5 V and − 5 V voltages at 500 kHz. Because metal–semiconductor structures play a crucial role not only for compensating the electronic devices but also in determining different functionalities in nano-structure devices. In the forward bias region (after 1.50 V), capacitance–voltage curves show a negative capacitance behavior. The experimental results obtained showed that the C–V and G/ω–V curves are strong functions of temperature and bias voltage especially in the accumulation region, and also the strong negative capacitance behavior is always accompanied after + 1.5 voltage for capacitance–voltage curves at all temperatures. That is, C–V characteristics are exhibited a behavior transition from the positive to negative value after 1.5 V. As the C values decreases, G/ω increases in the positive voltage region. This negative behavior for C–V curves in the forward bias regions is explainable by considering the losses of interface charge at occupied regions below Fermi level due to impact ionization processes. Also, these behavior values can also be attributed to the increase in the polarization particularly at low temperatures and the introduction of more carriers in the structure.

Negative capacitance effect of Cu–TiC thin film deposited by DC magnetron plasma

The quest for low power consumption devices with new functionalities has made the negative capacitance (NC) effect, the most captivating and studied phenomenon. The NC effect is observed in Cu–TiC thin film at a low-frequency range between 112.9 Hz and 2 kHz. The Cu–TiC thin film was deposited on Si (100) substrate by DC magnetron co-sputtering process and then annealed in a vacuum at different temperatures (100–600°C). The magnitude of NC increased from −0.016 to −27.5 µF after annealing. The NC behaviour is also observed in the forward biased region of the capacitance–voltage (C–V) characteristics. The current–voltage (I–V) characteristics reveal the decreasing static and dynamic resistance for higher annealed films. An improved electrical conductivity (27.70 × 103 to 384.62 × 103 S m−1) is evidenced with decreasing ideality factor (2.01–0.55) in the post-annealed films. The films were found to be polycrystalline from X-ray diffraction patterns with Cu and TiC phases. Raman studies have also confirmed the presence of Cu and TiC vibrational modes in all films. The intensity of C peaks detected at 1359 cm−1 (D peak) and at 1590 cm−1 (G peak) in the as-deposited film decreased after annealing. The annealing effect reduced the amount of unreacted carbon and contributed to form stoichiometric TiC from non-stoichiometric TiC.

A comprehensive study on Cu-doped ZnO (CZO) interlayered MOS structure

We present the structural, morphological, and electrical analysis of the copper-doped (wt 3%) ZnO (CZO) thin film grown with the RF sputtering system. CZO thin films were deposited on both soda–lime silicate glass and n-type (100)-oriented GaAs substrates. Following CZO thin-film deposition, samples were annealed at various temperatures ranging from 300 to 600 °C (by step 100 °C). Structural properties of the as-deposited CZO thin films grown on soda–lime silicate substrate and annealed at different temperatures (300 °C, 400 °C, 500 °C, 600 °C) were characterized by X-ray diffraction (XRD) measurements. It was seen that CZO thin film with 600 °C annealed temperature has the best peak compared to other annealed samples. Surface morphology of the CZO thin film with 600 °C annealed temperature was investigated by utilizing atomic force microscopy (AFM) and scanning electron microscopy (SEM) measurements. AFM and SEM results have shown that CZO with 600 °C annealed temperature has low surface roughness and good homogeneity. CZO thin film with 600 °C annealed temperature deposited on the n-GaAs substrate was used for electrical characterizations. C–V and G/ω–V forward and reverse bias measurements between − 2 and 4 V of Au/CZO/n-GaAs MOS structure with an annealing temperature of 600 °C were performed in the temperature range from 200 to 380 K (by step 30 K) at 1 MHz. It was observed to exhibit negative capacitance (NC) behavior for high-temperature region (320–380 K) from C–V measurements at forward bias voltage.

Negative capacitance phenomena in Au/SrTiO3/p-Si heterojunction structure

In this study, temperature- and frequency-dependent capacitance and conductance measurements of the Au/SrTiO3/p-Si heterojunction structure were examined. Strontium titanate (SrTiO3) thin films were deposited on cleaned p-type (100)-oriented silicon substrates using radio frequency (RF) magnetron sputtering method at a substrate temperature of 500 °C. The temperature-dependent reverse and forward bias C–V and G/ω$$-V$$ characteristics of the Au/SrTiO3/p-Si heterojunction structure was realized in the temperature range of 110–350 K (by step 30 K) at 1 MHz. The frequency-dependent reverse and forward bias C–V and G/ω$$-V$$ characteristics of the Au/SrTiO3/p-Si heterojunction structure was realized in the frequency range of 100–900 kHz (by step 100 kHz) at room temperature. It has been demonstrated that Au/SrTiO3/p-Si heterojunction structure exhibits negative capacitance (NC) behavior as a result of both temperature- and frequency-dependent capacitance measurements due to the reduction of interface charges, ionization states and series resistance in the forward bias voltage. In addition, it was shown that it exhibits an intersection point in the forward bias voltage of both temperature and frequency-dependent capacitance measurements. In temperature and frequency-dependent admittance spectroscopy measurements of Au/SrTiO3/p-Si heterojunction structure was observed NC phenomenon.

Concurrent Subthermionic and Strong Thermionic Transport in Inkjet‐Printed Indium Zinc Oxide/Silver Hybrid‐Channel Field‐Effect Transistors

AbstractSubthreshold slope of field‐effect transistors (FETs) less than the fundamental Boltzmann limit (60 mV dec−1 at 300 K) is demonstrated either using band‐to‐band tunneling or negative capacitance (NC) ferroelectric‐gate transistors. However, it is difficult to replicate both of these strategies in solution‐processed/printed FETs. Nonetheless, it is shown that the use of a metal–insulator–metal–semiconductor architecture alongside electrolyte gating can simultaneously create highly reproducible static negative capacitance behavior in printed FETs, resulting in subthermionic transport for over four decades of drain currents with a subthreshold slope as low as 16 mV dec−1, and thereafter a strong thermionic transport regime, characterized by an unprecedented On‐current of 195 µA µm−1, a transconductance of 215 µS µm, and a metal‐like On‐state resistance of only 96 Ω. The present device architecture is analogous to typical metal oxide semiconductor field‐effect transistor (MOSFET) geometry with printed amorphous indium zinc oxide (a‐IZO) as the semiconductor material, besides an additional metal layer on top of the a‐IZO channel that reduces the actual semiconducting channel dimension to the thickness of the printed a‐IZO layer. While the steep slope subthermionic transport regime can be utilized at wearable sensor interfaces, the high On‐currents/channel conductance can be used in optoelectronic applications, high‐current switches, and amplifiers.

Impact of PZT gate‐stack induced negative capacitance on analogue/RF figures‐of‐merits of electrostatically‐doped ferroelectric Schottky‐barrier tunnel FET

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency (), gain bandwidth product, transconductance generation factor and so on. The higher ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher ratio ensures lower bias power of an amplifier.

Ferroelectric negative capacitance

The capacitor is a key element of electronic devices and is characterized by positive capacitance. However, a negative capacitance (NC) behaviour may occur in certain cases and implies a local voltage drop opposed to the overall applied bias. Therefore, a local NC response results in voltage enhancement across the rest of the circuit. Within a suitably designed heterostructure, ferroelectrics display such an NC effect, and various ferroelectric-based microelectronic and nanoelectronic devices have been developed, showing improved performance attributed to NC. However, the exact physical nature of the NC response and direct experimental evidence remain elusive or controversial thus far. In this Review, we discuss the physical mechanisms responsible for ferroelectric NC, tackling static and transient NC responses. We examine ferroelectric responses to voltage and charge, as well as ferroelectric switching, and discuss proof-of-concept experiments and possibilities for device implementation. Finally, we highlight different approaches for the optimization of the intrinsic NC response to maximize voltage amplification. Ferroelectrics-based materials can display a negative capacitance (NC) effect, providing an opportunity to implement NC in electronic circuits to improve their performance. In this Review, the authors discuss static and transient NC responses in ferroelectrics and highlight proof-of-concept experiments and possibilities for device implementation.

Voltage and frequency dependence of negative capacitance behavior in a Graphene-TiO2 nanocomposite photoanode based on quantum dot sensitized solar cells

In this letter, we investigated negative capacitance (NC) effect in nanocomposite based quantum dot sensitized solar cells. TiO2 and graphene-TiO2 nanocomposite photoanode based on quantum dot sensitized solar cells (QDSSCs) were fabricated and the capacitance-voltage (C–V), capacitance-frequency (C-f) and conductance-voltage (G/ω-V) characteristics were studied by attention the series resistance (Rs) effect. Admittance spectroscopy of QDSSCs were measured in a variable voltage and frequency ranges of (−2 V) - (+2 V) and 10 kHz-10 MHz, respectively. Capacitance values are exhibited a behavior transition from the positive to negative value after 50 kHz. As the capacitance values decreases, conductance increases in the NC region. Negative capacitance effect of meaning that QDSSC indicates an inductive behavior. Inductive behavior, which means that electrons injects from fluorine-doped tin oxide (FTO) conductive glass electrode to photoanode (graphene-TiO2). Also, NC phenomenon has not form significant effect on Rs.