Abstract

AbstractSubthreshold slope of field‐effect transistors (FETs) less than the fundamental Boltzmann limit (60 mV dec−1 at 300 K) is demonstrated either using band‐to‐band tunneling or negative capacitance (NC) ferroelectric‐gate transistors. However, it is difficult to replicate both of these strategies in solution‐processed/printed FETs. Nonetheless, it is shown that the use of a metal–insulator–metal–semiconductor architecture alongside electrolyte gating can simultaneously create highly reproducible static negative capacitance behavior in printed FETs, resulting in subthermionic transport for over four decades of drain currents with a subthreshold slope as low as 16 mV dec−1, and thereafter a strong thermionic transport regime, characterized by an unprecedented On‐current of 195 µA µm−1, a transconductance of 215 µS µm, and a metal‐like On‐state resistance of only 96 Ω. The present device architecture is analogous to typical metal oxide semiconductor field‐effect transistor (MOSFET) geometry with printed amorphous indium zinc oxide (a‐IZO) as the semiconductor material, besides an additional metal layer on top of the a‐IZO channel that reduces the actual semiconducting channel dimension to the thickness of the printed a‐IZO layer. While the steep slope subthermionic transport regime can be utilized at wearable sensor interfaces, the high On‐currents/channel conductance can be used in optoelectronic applications, high‐current switches, and amplifiers.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call