Negative Bias Temperature Stress Research Articles

P‐15: The Back‐channel Effect in Low Temperature Poly‐Si Thin Film Transistors

This paper addresses the mechanism of the back‐channel effect on TFTs (Thin Film Transistors) and proposes novel methods for characterizing and improving the stability of driving TFT devices, including back‐channel and back‐voltage testing. In comparison to routine sticking image and negative bias temperature stress testing, our methods aim to minimize the impact of intrinsic material fluctuations, allowing for independent measurement of the back‐channel effect on TFT device electrical characteristics. We also offer an enhanced option (N2 Plasma treatment of PI surface), that have been used for better the performance of products.

Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (>32 cm2 V−1 s−1) along with a current on/off ratio of approximately 108 and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility.

Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (VTH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a VTH shift of -0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

High-pressure H2O post-annealing for improving reliability of LTPS and a-IGZO thin-film transistors within a coplanar structure

Improving reliability of low-temperature polycrystalline silicon (LTPS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), components of low-temperature polycrystalline silicon and oxide (LTPO), is crucial for fabricating high-performance and high-stability LTPS and oxide semiconductor-based electronics and display products. However, improving the reliability of these TFTs simultaneously in a uniform and effective manner within a coplanar structure is challenging. In this work, high-pressure H2O post-annealing (H2O HPPA) as a post-treatment for LTPS and a-IGZO TFTs within a coplanar structure are proposed to improve the uniformity and stability of the electrical characteristics simultaneously. It was demonstrated that oxygen and hydrogen in the HPPA-passivated defect state at the channel/gate dielectric layer interfaces and bulk gate dielectric layers of LTPS and a-IGZO TFTs considerably improve the uniformity and stability of the electrical performance and morphologies of the interfaces. Thus, the distribution of electrical characteristics (mobility, threshold voltage, and subthreshold swing) in LTPS and a-IGZO TFTs was reduced by more than 2-fold, and the trap charge densities at their interfaces and bulk gate dielectric layers were reduced by approximately 1.6-fold. Furthermore, the threshold voltage shift was decreased in both LTPS and a-IGZO-TFTs fabricated with H2O HPPA under negative and positive bias temperature stresses, respectively. The proposed H2O HPPA method can effectively facilitate the industry-level application of LTPS and oxide semiconductor-based electronics and display electronics.

AC-Stress Degradation and Its Anneal in SiC MOSFETs

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress.

Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress

In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ([Formula: see text]) and interface traps ([Formula: see text]) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of [Formula: see text] neutralization and [Formula: see text] passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.

P‐30: Thermally Activated and Field‐Enhanced Diffusion of Dopants in a‐InGaZnO TFTs Under Circuit Operations and Correlation to Device Stabilities

The spatial distribution of the donor dopant and the source‐drain resistance (RSD) in oxide Thin Film Transistor (TFT) for display backplane is usually considered to be determined by the device structure and the process. This work shows that the dopant concentration of lateral distribution of thermal equilibrium carrier concentration n0(y) may vary dynamically depending on the operation conditions during circuit operation and thermally‐activated and field‐enhanced diffusion of dopants in InGaZnO (IGZO) was found as a physical cause. In actual Organic Light‐Emitting Diode (OLED) backplane circuit operation, the reliability degradation conditions of IGZO TFTs were summarized into three conditions: Negative Bias Temperature Stress (NBTS), Constant Voltage Stress (CVS), and Drain‐to‐Source Voltage (VDS)‐sweep, and as a result of analyzing TFT device reliability, dopant diffusion occurred as the temperature increased, and the lateral field increased, resulting in RSD increase and channel resistance decrease. This causes degradation of device characteristics accumulated during circuit operation and shows various degradation patterns. It is connected to the existing Positive Bias Stress (PBS) and Negative Bias Stress (NBS) degradation mechanisms and other hot carrier degradation and self‐heating. In particular, it has been reported that dopant diffusion and source‐drain series resistance (RSD) change occur under high VGS, high VDS, and short channel conditions, resulting in permanent failure of the IGZO TFT channel by forming positive feedback.

Impact of post-nitridation annealing in CO2 ambient on threshold voltage stability in 4H-SiC metal-oxide-semiconductor field-effect transistors

The combination of NO annealing and subsequent post-nitridation annealing (PNA) in CO2 ambient for SiO2/SiC structures has been demonstrated to be effective in obtaining both high channel mobility and superior threshold voltage stability in SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs). N atoms on the SiO2 side of the SiO2/SiC interface incorporated by NO annealing, which are plausible causes of charge trapping sites, could be selectively removed by CO2-PNA at 1300 °C without oxidizing the SiC. CO2-PNA was also effective in compensating oxygen vacancies in SiO2, resulting in high immunity against both positive and negative bias-temperature stresses.

Enhancing Reliability and 2 mm-Axial Mechanical Bending Endurance by Gate Insulator Improvements in Flexible Polycrystalline Silicon TFTs

In this study, the electrical performance and bending stress endurance of flexible low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) are enhanced by increasing the helium concentration (1500 sccm) during gate insulator (GI) manufacture to create a high-quality GI device. Experimental results confirm that the subthreshold swing (S.S.) and mobility of these new &#x201C;high-flow&#x201D; devices are better than those with a lower helium concentration, which we term &#x201C;low-flow&#x201D; devices. The flow of helium gas is increased to achieve a better-quality oxide layer. The energy-dispersive X-ray spectroscopy (EDS) line data show a clear enhancement in oxygen content in the devices under this helium gas process. After mechanical compression and tensile bending stresses of 100000 iterations in the channel width-axis direction, perpendicular to the channel, with bending at <inline-formula> <tex-math notation="LaTeX">${R} = {2}$ </tex-math></inline-formula> mm, the modified GI devices with their more Si-O bond content exhibit less stress damage in the GI layer than do low-flow devices. As a result, this new manufacturing condition can effectively reduce the electrical degradation after negative-bias temperature stress (NBTS), and improve the overall electrical performance.

Investigation of degradation mechanism after negative bias temperature stress in Si/SiGe channel metal–oxide–semiconductor capacitors induced by hydrogen diffusion

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

Poly‐Si Thin‐Film Transistors on Polyimide Substrate for 1 mm Diameter Rollable Active‐Matrix Organic Light‐Emitting Diode Display

Thin‐film transistor (TFT) backplanes on polyimide (PI) substrate are widely used for foldable active‐matrix organic light‐emitting diode (AMOLED) display. The low‐temperature poly‐Si (LTPS) TFTs on PI substrate for AMOLED displays use the inorganic interlayer (ITL) of SiO2/SiNx deposited on the poly‐Si. Herein, a flexible ITL, very thin SiNx/organic PI layer stack, is introduced to improve both mechanical flexibility and environmental stability of LTPS TFT backplane on PI substrate. The electrical stabilities of LTPS TFT with various ITLs are studied such as positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS). It is found that the LTPS TFTs are stable under PBTS and/or NBTS. However, the results on mechanical stability depend on the ITL used. The LTPS TFTs with hybrid ITL (SiNx/organic PI) and organic ITL(PI) are stable under mechanical stress because these TFTs have much less strain under mechanical bending because of the low Young's modulus of PI material. In addition, environmental stabilities of the LTPS TFTs with hybrid ITL is stable at 85 °C and 85% humidity in dark. Therefore, the LTPS TFTs with hybrid ITL are very suitable for rollable active matrix displays.

Effects of polyimide curing on image sticking behaviors of flexible displays

Flexible displays on a polyimide (PI) substrate are widely regarded as a promising next-generation display technology due to their versatility in various applications. Among other bendable materials used as display panel substrates, PI is especially suitable for flexible displays for its high glass transition temperature and low coefficient of thermal expansion. PI cured under various temperatures (260 °C, 360 °C, and 460 °C) was implemented in metal–insulator–metal (MIM) capacitors, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT), and actual display panels to analyze device stability and panel product characteristics. Through electrical analysis of the MIM capacitor, it was confirmed that the charging effect in the PI substrates intensified as the PI curing temperature increased. The threshold voltage shift (ΔVth) of the samples was found to increase with rising curing temperature under negative bias temperature stress (NBTS) due to the charging effect. Our analyses also show that increasing ΔVth exacerbates the image sticking phenomenon observed in display panels. These findings ultimately present a direct correlation between the curing temperature of polyimide substrates and the panel image sticking phenomenon, which could provide an insight into the improvement of future PI-substrate-based displays.

Investigation of degradation behavior under negative bias temperature stress in Si/Si0.8Ge0.2 metal-oxide-semiconductor capacitors

In this paper, capacitance and conductance characteristics are used to explain reliability issues in metal-oxide-semiconductor capacitors (MOSCAPs) with a silicon-germanium (SiGe) channel. The SiGe channel devices are also comprehensively compared to traditional Si channel devices. After negative bias temperature stress, both exhibit flat-band voltage (V FB) shifts in the negative direction and a rise in the conductance hump. Generally, the process of Si devices is more stable than SiGe devices, resulting in the interface quality of Si MOSCAPs being better due to lattice constant matching at the interface. However, it is noteworthy that the degradation of Si MOSCAPs is more serious than that of Side MOSCAPs. Therefore, this study quantitatively extracts the interface defects and illustrates the generation of interface defects with a reaction-diffusion model. In addition, the difference in the injected energy level is used to explain the difference in the VFB shift.

Improvement of metal-oxide films by post atmospheric Ar/O2 plasma treatment for thin film transistors with high mobility and excellent stability

Metal-oxide thin-film transistors (MO TFTs) with suitable device performances such as high field-effect mobility (μ FE), low subthreshold swing, high ON/OFF current ratio, and excellent stability under bias stress are of increasing attention for the applications to displays and flexible electronics. Here, we introduce the effect of post atmospheric Ar/O2 plasma (AAP) on spray-pyrolyzed MO film and its role in realizing the high-performance TFT. To better understand the physicochemical mechanism, the spectroscopic, morphologic, and electrical properties of the MO films were studied. From the X-ray photoelectron spectroscope (XPS) results, the composition ratios for Zn:La:O in AAP-treated LaZnO are 4.97:1.00:7.65 before treatment, 5.01:1.00:8.58 upon 5 cycles treatment, and 4.68:1.00:9.72 for 10 cycle treatment. The LaZnO TFT mobilities for 0, 5 and 10 cycles treatment are 8.64, 20.13, and 8.96 cm2 V−1 s−1, respectively. The AAP-treatment on the MO layer could improve the saturation mobility of ZnO, LaZnO, HfZnO, and LiZnO TFTs from 11.65, 8.95, 4.46, and 33.50 cm2 V−1 s−1 to 23.64, 20.13, 12.56, and 48.47 cm2 V−1 s−1, respectively. Furthermore, the optimal TFT shows excellent stability under positive (negative) bias temperature stress (PBTS and NBTS) with a negligible threshold voltage shift.

Improved charging phenomenon with a modified barrier structure for flexible displays fabricated on polyimide substrates

In a previous study, the authors investigated that abnormal Vth behaviour could occur due to polyimide charging when a voltage was applied to the gate in thin film transistors fabricated on polyimide substrates. The authors propose a barrier structure that could prevent this charging effect when fabricating flexible thin film transistors on polyimide substrates. The barrier layer was changed to an SiOCH/SiO2 double layer to reduce the influence of fluorine ions generated in PI by negative bias temperature stress. To confirm the effect of the SiOCH layer, Al/PI/SiO2/Al, Al/PI/SiOCH/SiO2/Al metal-insulator-metal capacitors were fabricated and electrical properties were measured. When bias stress was applied, changes in current and capacitance were observed only in the device with a single SiO2 barrier layer. In addition, it was confirmed through secondary ion mass spectrometry measurements that the Si–CH3 bonds in the SiOCH layer were replaced with Si–F bonds by the fluorine ions originating from PI. It was also verified that the abnormal behaviour of Vth did not occur after negative bias temperature stress of the thin film transistor fabricated using an SiOCH/SiO2 double layer.

Investigation of Degradation Behavior During Illuminated Negative Bias Temperature Stress in P-Channel Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a study of physical mechanisms is introduced to describe an abnormal phenomenon in transfer characteristics while p-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) were subjected to a negative bias temperature stress (NBTS) in an illuminated environment. In general, under NBTS, the transfer characteristics exhibits a negative shift of threshold voltage and a degradation of subthreshold swing. Here, however, experimental results reveal that the degree of degradation is different after NBTS is applied to poly-silicon TFTs in a darkened and in an ultraviolet condition. This variation is mainly a result of the light-generated electrons recombining with the inversed holes, and leading to a lower degree of degradation. Moreover, we found that the influence of the UV light is an edge effect at different channel lengths. This letter investigates the illumination effect in LTPS TFTs during NBTS, and the phenomenon is clarified by electrical measurements and by trap state extraction.

Finding the cause of degradation of low-temperature oxide thin-film transistors

We report the cause of degradation of low-temperature amorphous indium-gallium-zinc-oxide (a-IGZO) coplanar thin-film transistors (TFTs). As the deposition temperature of the buffer layer was changed from 400 to 200 °C, the field-effect mobility decreased considerably from 15 to 3 cm2 V−1 s−1, the subthreshold swing (SS) increased from ~ 150 to 280 mV dec−1, the threshold voltage shift (ΔVth) under negative bias temperature stress (NBTS) increased from − 0.27 to − 0.33 V, and ΔVth under a positive bias temperature stress (PBTS) increased significantly from 0 to 4.9 V. From the results of high-resolution transmission electron microscopy (HR-TEM) and X-ray reflectivity (XRR), the poor roughness created by sputtering damage of the interface between the gate insulator (GI) and the a-IGZO is the cause of degradation. In addition, through an atomic probe tomography (APT) analysis, the reason low-temperature TFTs have poorer PBTS stability than NBTS is carefully to be due to zinc (Zn)-related defects that create ionized oxygen vacancies. Based on these results, we introduce strategies for realizing low-temperature oxide TFTs using vacuum process. Please confirm if the author names are presented accurately and in the correct sequence as given name, middle name/initial, family name. Also, kindly confirm the details in the metadata are correct. We confirmed all author names. Please check and confirm that the authors and their respective affiliations have been correctly identified and amend if necessary. We checked all authors and their affiliations.

Effect of PECVD Gate SiO2 Thickness on the Poly-Si/SiO2 Interface in Low-Temperature Polycrystalline Silicon TFTs

This study investigates the effect of the gate SiO2 thickness (80, 100, and 130 nm) deposited by plasma enhanced chemical vapor deposition on the interface and reliability characteristics of low-temperature polycrystalline silicon thin film transistors. Field effect mobility is significantly degraded as the gate oxide thickness decreases. The border trap density (Nbt) extracted from capacitance–voltage hysteresis exhibits no trend with respect to the gate oxide thickness, indicating that field effect mobility is not governed by Nbt. The quantitative interface trap density (Nit) was obtained using a 3-terminal charge pumping method; results showed that Nit decreased as the gate oxide thickness increased. However, it was observed that the threshold voltage (Vth) shift during negative bias temperature stress is worse in the thicker SiO2 film, which has a low Nit. After activation annealing, the amount of hydrogen in the gate oxide increased as the thickness of the insulator was raised. This in turn caused a larger shift in Vth. To validate this mechanism, the amount of hydrogen with respect to the device depth was analyzed via secondary ion mass spectroscopy. It has been found that the presence of more hydrogen concentration in the SiO2 film and the interface to the thicker SiO2 results in more Vth shifts under bias temperature stress.

Influence of Si\u2013In\u2013Zn\u2013O/Ag/Si\u2013In\u2013Zn\u2013O Electrode on Amorphous Si\u2013Zn\u2013Sn\u2013O Thin Film Transistors

Amorphous SiZnSnO (a-SZTO) thin film transistors (TFTs) have been reported with transparent Si–In–Zn–O/Ag/Si–In–Zn–O (SIZO OMO) source/drain (S/D) electrodes. The characteristics of ITO and SIZO OMO electrodes were compared with conventional metal electrode of Ti/Al. The SZTO TFT with SIZO OMO electrode showed high field effect mobility of 17.69 cm2/Vs, threshold voltage of 4.05 V and low sub-threshold swing of 0.33 V/decade. The stability of a-SZTO TFTs with SIZO OMO electrode was measured ∆VTH = 1.4 V at 333 K, and − 20 V for 7200 s under negative bias temperature stress (NBTS).