Negative Bias Temperature Instability Research Articles

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Experiments have done with the goal to obtain data for modeling. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.

Improvement of negative bias temperature instability of LTPS TFTs by high pressure H2O annealing

In this study, high pressure H2O annealing (HPA) was performed to improve the reliability of low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate. Due to the low heat resistance of the PI substrate, the pressure was high to reduce the temperature of the heat treatment. HPA was performed at 130 °C and 0.3 Mpa in an H2O ambient for 2 h. After HPA treatment, the threshold voltage (VT) shifted to the positive direction from −2.27 V to −1.75 V, and the hysteresis (ΔVT) decreased from 0.67 V to 0.24 V. The density of states (DOS) measurement shows that the interface trap decreased after HPA processing, hence, it is assumed that stability for bias stress has improved. Before and after HPA, the VT shift for negative bias temperature instability (NBTI) stress was 1.19 V and 0.2 V, respectively. After HPA treatment, ΔVT decreased significantly for bias stress. It seems that the decomposed oxygen from H2O diffused to the gate insulator and combined with Si to reduce the oxygen vacancy. The strength of the gate insulator improved after HPA.

Comparative Analysis of Hot Carrier Degradation (HCD) in 10-nm Node nMOS/pMOS FinFET Devices

In 10-nm node core FinFETs, we analyzed the cause of higher hot carrier degradation (HCD) in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain materials, which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle (MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the pure HCD mechanisms to occur more in pFinFETs, which has higher temperature than nFinFETs. However, in pFinFETs, unlike nFinFETs, interface traps can be generated due to negative-bias temperature instability (NBTI) that occurs by the reaction between inversion holes and electrons of Si-H bonds. Also, since NBTI deteriorates more as the temperature increases, the phenomenon of higher degradation in pFinFET than nFinFET can be explained with the NBTI mechanism. Therefore, we propose an additional NBTI mechanism that is caused by high device temperature in pFinFETs even in the HCD condition. In addition, the main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that NBTI is dominant in pFinFETs. Finally, NBTI that can occur in the HCD condition was predicted through technology computer-aided design (TCAD) simulation. As a result, degradation due to pure hot carriers without NBTI occurs more in nFinFETs than in pFinFETs.

Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells

In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VTH compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations.

Aging-Aware Parallel Execution

Computation has been pushed to the edge to decrease latency and alleviate the computational burden of the IoT applications in the cloud. However, the increasing processing demands of edge applications make necessary the employment of platforms that exploit thread-level parallelism (TLP). Yet, power and heat dissipation rise as TLP inadvertently increases or when parallelism is not cleverly exploited, which may be the result of the nonideal use of a given parallel program interface (PPI). Besides the common issues, such as the need for more robust power sources and better cooling, heat also adversely affects aging, accelerating phenomenons, such as negative bias temperature instability (NBTI) and hot-carrier injection (HCI), which further reduces processor lifetime. Hence, considering that increasing the lifespan of an edge device is key, so the number of times the application set may execute until its end-of-life is maximized, we propose BALDER. It is a learning framework capable of automatically choosing optimal configuration executions (PPI and number of threads) according to the parallel application at hand, aiming to maximize the tradeoff between aging and performance. When executing ten well-known applications on two multicore embedded architectures, we show that BALDER can find a nearly optimal configuration for all our experiments.

A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes

The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT) based health monitoring system. The cell executes improved write and read ability using data-dependent feedback cutting and read decoupled access path mechanism respectively. The write and read stabilities of proposed cell are $$2.67\times$$ and $$1.98\times$$ higher than the conventional 6T cell with $$1.53\times$$ area overhead. Moreover, the improved soft error tolerance and better reliability against negative bias temperature instability (NBTI) of proposed 11T SRAM cell as compared to other considered cells make it suitable for the bio medical implant. A low-power double adjacent bit error detection and correction (DAEDC) scheme is proposed to further improve the robustness of designed 1 Kb bit-interleaved memory against the soft error occurrence. The leakage power of proposed cell is controlled by the stacking devices used in its cross-coupled inverter pair and the column based read ground signal (RGND) further controls the unnecessary bit line switching power of the array.

Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.

Bias stress instability of LTPS TFTs on flexible substrate with activation annealing temperature

In this paper, we identified the defect state of p-channel low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate that is distributed differently in the interface and channel areas depending on the activation annealing temperature, as well as observed the effect on the threshold voltage (VT) and reliability. To verify the effect of the process temperature on the performance of the LTPS TFTs, an activation heat treatment was conducted at 400 °C, 370 °C and 340 °C. More defects were distributed in the interface and channel area of LTPS TFTs with low heat treatment temperature, resulting in VT formed at a higher voltage. After the negative bias temperature instability (NBTI) test, the VT shifted in the negative voltage direction and moved −0.13 V, −0.51 V and −0.72 V from LTPS TFTs with high activation annealing temperature. In the hot carrier instability (HCI) test, VT also shifted to the negative direction of −0.19 V, −0.51 V, and −1.07 V. The defects distributed in the interface and channel areas that are not curated or activated due to the low activation annealing temperature caused instability under the bias stress.

On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance

Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable and free from half select issues. We investigated all the circuit simulations using 65nm CMOS technology. The proposed 10T cell has a higher critical charge and lower soft error rate (SER) as compared to other SRAM cells. To better assess, we introduced a bit read failure (BRF) at read operation and observed that the BRF of the proposed 10T cell is significantly reduced as compared to the other considered SRAM cells at 0.15V supply. The leakage power, write power-delay-product, and read power-delay-product of the proposed 10T cell is $0.1\times $ , $0.21\times $ , and $3.13\times $ , respectively as compared to the conventional 6T cell at 0.4V supply. The proposed cell offers $4\times $ , $1.15\times $ and $1.66\times $ higher read, hold and write margin, respectively, as compared to 6T cell at 0.4V supply voltage. The simulation result shows that the HSNM, WSNM, and RSNM are decreased by 0.31%, 0.13%, and 0.08%, respectively, with the proposed 10T cell while 6T cell reduces 3.21%, 0.43%, and 8.62%, respectively, after 10 years of stress time. We have also introduced an on-chip adaptive VDD scaled reconfigurable architecture compared to the conventional array architecture design to reduce 97.04% and 92.17% hold power of unselected cells during read and write operation of the selected cell, respectively for the proposed 10T cell.

Impacts of O2 Plasma on Negative Gate Bias Stress Instability of Tunnel Thin-Film Transistor

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage (VTH) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to -0.82 V, respectively. The degradation of on-state current is also improved significantly from -87% to -40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step VTH shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C.

7‐1: Distinguished Paper: Alleviation of Abnormal NBTI Phenomenon in LTPS TFTs on Polyimide Substrate for Flexible AMOLED

This letter investigates the negative‐bias temperature instability (NBTI) behavior of p‐channel low‐temperature polycrystalline silicon thin‐film transistors (LTPS TFTs) on plastic substrate. The measurements reveal that the threshold‐voltage positive shift is highly correlated to the passivation of grain‐boundary trap states. By applying the established phenomenon such as NBTI recovery and H diffusion from PI substrate, a new model is introduced to explain mechanism and verified by the experiment. With the thick buffer & bottom metal layer or newly processed PI substrate, we succeeded in adjusting the NBTI behavior of LTPS TFTs on plastic substrate.

Improved Long-Term Stability of Low-Temperature Polysilicon Thin-Film Transistors by Using a Tandem Gate Insulator with an Atomic Layer of Deposited Silicon Dioxide

In this study, we report a substantial improvement in the long-term stability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) with a tandem gate insulator composed of silicon dioxide (SiO2) deposited by using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD). Negative-bias temperature instability (NBTI) tests showed that threshold-voltage (ΔVth) shifts were significantly smaller than when only a plasma-enhanced chemical vapor deposition (PECVD) structure was used. We believe that the unique stoichiometric characteristics and the reduction in the interfacial trap density (Dit) produced by the SiO2 gate insulator that had been fabricated using ALD enhanced the long-term stability of the LTPS TFTs. These results suggest a tandem structure gate insulator with high-quality ALD-based SiO2 thin film can provide an important improvement in the characteristics of the p-channel LTPS TFTs required for advanced active matrix organic light-emitting diodes (AMOLEDs) applications.

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

Accelerated Testing of SiC Power Devices under High-Field Operating Conditions

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling

Negative Bias Temperature Instability (NBTI) effect occurs in a PMOS transistor when turned ON leading to threshold voltage degradation. As sub-threshold leakage is significant in nanoscale CMOS circuits, input vector control can be employed wherein a Minimum Leakage Vector (MLV) is applied to the circuit during idle periods. In such a case, the ON PMOS transistors on the critical path are subject to NBTI stress for prolonged periods. Transistors can recover from stress when turned OFF. Based on this observation, we propose a vector cycling based leakage/NBTI co-optimization: a pair of MLVs are identified such that when applied alternately, on the critical path, PMOS transistors activated by one vector are turned OFF by the other vector. We employ Simulated Annealing (SA) for stochastic search of the first vector followed by back tracking to identify the second vector. Experimental results for a subset of ISCAS85 benchmarks implemented in 45 nm technology demonstrate the feasibility of vector cycling approach. When compared to leakage-only optimization, NBTI-only optimization, and co-optimization, on average, vector cycling yields 11, 3, and 6 percent NBTI improvements with 18, -9, and 4 percent leakage overheads respectively. The average area and dynamic power overheads are 13.78 and 0.15 percent respectively.

Investigation of HCD- and NBTI-Induced Ultralow Electric Field GIDL in 14-nm Technology Node FinFETs

The generation of defect states in p-MOSFETs under negative bias temperature instability (NBTI) has been extensively discussed in previous literature. However, only a few studies have discussed the relationship between interface defects and off -state leakage. Therefore, this article analyzes the impact of interface defects generated by NBTI on gate-induced drain leakage (GIDL). In general, GIDL is generated through band-to-band tunneling (BTBT) at large gate-to-drain bias ( ${V}_{\text {GD}}$ ). In this article, NBTI causes an increase in GIDL at extremely low ${V}_{\text {GD}}$ . By measuring at different temperatures and comparing the GIDL generated from hot carrier degradation (HCD), it was confirmed that the GIDL would still be generated through trap-assisted tunneling (TAT) and thermal excitation at an extremely low ${V}_{\text {GD}}$ .

Aging-Aware Context Switching in Multicore Processors Based on Workload Classification

As transistor dimensions continue to shrink, long-term reliability threats, such as Negative Bias Temperature Instability, affect multicore processors lifespan. This letter proposes a load balancing technique, based on the rate of integer and floating-point instructions per workloads. This technique classifies workloads into integer-majority and floating-point-majority classes and migrates workloads among cores in order to relax the stressed execution units. The context switching feature of operating system is employed to reduce implementation and performance overheads of the proposed technique. According to the simulations, the proposed technique reduces the aging rate of a multicore processor by about 35 percent in 10 years of system operation. This is achieved by only 7 percent performance penalty.

Recovery investigation of NBTI-induced traps in n-MOSFET devices

Conducting negative bias temperature instability (NBTI) stress/recovery experiments on n-type metal-oxide-semiconductor-field-effect-transistors (n-MOSFETs), we have been able to reveal the existence of turn around phenomenon during stress phase. At first stage of stress, threshold voltage (Vth) shifts positively, followed later by a negative shift. Furthermore, recovery phase has shown, for the first time, the contribution of three components to Vth shift (ΔVth) in n-MOSFET. One component is permanent (ΔVthP) and dominated by interface traps, created during stress at the Si/SiO2 interface. The other components are oxide traps, generated in the interfacial oxide region. Both traps are positively charged; one is cyclic (ΔVthC), while the other is totally recoverable (ΔVthR).

Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.