On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance

Abstract

Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable and free from half select issues. We investigated all the circuit simulations using 65nm CMOS technology. The proposed 10T cell has a higher critical charge and lower soft error rate (SER) as compared to other SRAM cells. To better assess, we introduced a bit read failure (BRF) at read operation and observed that the BRF of the proposed 10T cell is significantly reduced as compared to the other considered SRAM cells at 0.15V supply. The leakage power, write power-delay-product, and read power-delay-product of the proposed 10T cell is $0.1\times $ , $0.21\times $ , and $3.13\times $ , respectively as compared to the conventional 6T cell at 0.4V supply. The proposed cell offers $4\times $ , $1.15\times $ and $1.66\times $ higher read, hold and write margin, respectively, as compared to 6T cell at 0.4V supply voltage. The simulation result shows that the HSNM, WSNM, and RSNM are decreased by 0.31%, 0.13%, and 0.08%, respectively, with the proposed 10T cell while 6T cell reduces 3.21%, 0.43%, and 8.62%, respectively, after 10 years of stress time. We have also introduced an on-chip adaptive VDD scaled reconfigurable architecture compared to the conventional array architecture design to reduce 97.04% and 92.17% hold power of unselected cells during read and write operation of the selected cell, respectively for the proposed 10T cell.