Negative Bias Temperature Instability Degradation Research Articles

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability (NBTI) can be attributed to three mutually uncoupled physical mechanisms, i.e., the generation of interface traps (ΔV IT), hole trapping in pre-existing gate oxide defects (ΔV HT), and the generation of gate oxide defects (ΔV OT). In this work, the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate (HKMG) process is thoroughly studied. The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature. The effects of the three underlying subcomponents are evaluated by using the comprehensive models. It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress. Moreover, the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted. The dependence of operating lifetime on stress bias and temperature is also discussed. It is observed that NBTI lifetime significantly decreases as the stress increases. Furthermore, the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

An equivalent circuit model of NBTI effect for short-channel P-MOSFET

An equivalent circuit model of the negative bias temperature instability (NBTI) effect in 65 nm P-MOSFET is presented in this paper. Based on an existing P-MOSFET model of a 65 nm CMOS foundry PDK (Process Design Kit) and several basic electrical components and arithmetic cells in the EDA (Electronics Design Automation) library, an equivalent circuit model for NBTI degradation has been achieved. The electrical components and arithmetic cells include voltage source, voltage-controlled voltage source, voltage-controlled current source, adder, and multiplier. The equivalent circuit model includes five tunable input parameters: gate width (W), gate length (L), temperature (temp), stress time (t), and process corner (typical/fast/slow). The model takes into account the effects of drain-source, drain-gate, and gate-source voltage stress states. The effect of process corner on NBTI is also considered. The simulation results show that the performance curve of this P-MOSFET equivalent circuit model is consistent with the measured data in some published literature. This equivalent circuit model can be utilized for long-term reliability IC design.

Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity.

Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET.

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = −1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices.

An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic

Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of Very Large-Scale Integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in Deep Sub Micron (DSM) regime is Negative- Bias Temperature Instability (NBTI). NBTI effect increases the threshold voltage of p-channel Metal Oxide Semiconductor (PMOS) device over the time and affects the different characteristics of the device. As a result, circuit delay exceeds the design specification and there may be timing violations or logic failure. Different performance parameters are observed under NBTI effect for different logic gates. Methods: This paper presents an impact of NBTI at 22nm Berkeley short-channel IGFET model4 (BSIM4) Predictive Technology Model (PTM) for Complementary Metal Oxide Semiconductor (CMOS) logic gates. Reliability simulations are utilized to evaluate the amount of gradual damage in PMOS device due to NBTI effect. Results : The impact of NBTI degradation is checked for various CMOS logic gates using Mentor Graphics’s Eldo circuit simulator. Output voltage and drain current are reducing over the time under NBTI effect. Conclusion: NBTI degradation increases the threshold voltage of PMOS device over time and affects the different characteristics of the device.

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

Design and Simulation for NBTI Aware Logic Gates

Reliability of the electronic circuits is one of the most prominent factor in the development of very large-scale integration (VLSI) industry. Huge demand for compact size and high performance of electronic devices leads the excessive scaling of the transistor. Aggressive scaling of transistor in ultra-deep submicron regime arises the problem of short channel effects (SCEs) which is the major reason for subthreshold leakage and reliability issues. Negative input voltage to p-channel metal oxide semiconductor (PMOS) transistor causes interface traps at silicon dioxide and silicon substrate interface which leads to increase in the threshold voltage of the transistor and degrades the circuit performance. The design parameters exceed the design specification and causes the variations in timing due to negative bias temperature instability (NBTI) degradation that results logic failure. This paper presents the impact of reliability variations on 32 nm complementary metal oxide semiconductor (CMOS) predictive technology model (PTM) and 20 nm multi-gate PTM fin-shaped field effect transistor (FinFET) circuits. NBTI degradation of various circuits are evaluated with the help of Cadence’s virtuoso tool containing Spectre native reliability simulator. Simulation results are showing that NBTI degradation causes variations in threshold voltage and alters the output performance.

Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics

ABSTRACT Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined impact’ of NBTI degradation along with the process, voltage and temperature (PVT) variations on SRAM metrics. These issues impact the performance of SRAM (Static Random Access Memory) cell in many ways but the two main dynamic metrics are critical read-stability and write-ability. The dynamic metrics can, in turn, be characterised by their static metrics, that determine the static noise margins (SNM) of SRAM. The dynamic metrics were analysed for symmetric and asymmetric NBTI degradation of two inverters of SRAM. NBTI degradations were incorporated on the pull-up transistors of SRAM cell. Furthermore, results of the correlated performance metrics are presented for varied data storage patterns in SRAM cell over its lifetime. This analysis aims to provide an insight into the effects of integrated PVT and NBTI degradation on SRAM cell performance, enabling robust designs and help designers at the early stage of design to mitigate system failure.

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor

With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

A statistical study into reliability of FPGA implemented circuits: Simulation and modelling

In this work, we report on the development of a methodology to study the reliability of digital circuits implemented in FPGA. For this, the design and simulation tools have been extended to introduce aging. The aging laws for Look-Up Tables, describing the drifts in the propagation time, caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms, have been integrated into the simulation environment by introducing additional variables and equations. Moreover, the study has been further extended by considering the statistical dispersion in the failure time due to different sources of dispersion. Furthermore, an analytical and a statistical model of the failure time of the digital circuit as a function of the clock frequency, aging law parameters and dispersion parameters have been proposed. Finally, the developed methodology has been applied to two different digital circuits implemented in FPGA.

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent $n$ from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift ( ${\Delta }$ V $_{T}$ ), pre-existing traps ( ${\Delta } {N} _{\mathrm {HT}}$ ), generated traps, and their relative contributions were studied. The time exponents of ${\Delta }$ V $_{T}$ , the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B2H6-based W-filling metal, a 34% reduction in the fresh interface states, reduced ${\Delta }$ V $_{T}$ , and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of ${\Delta } {N} _{\mathrm {HT}}$ is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.

Impacts of O2 Plasma on Negative Gate Bias Stress Instability of Tunnel Thin-Film Transistor

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage (VTH) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to -0.82 V, respectively. The degradation of on-state current is also improved significantly from -87% to -40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step VTH shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C.

Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.

Design Principles of Self-Compensated NBTI-Free Negative Capacitor FinFET

The Landau field-effect transistors have been previously investigated to lower the power dissipation of integrated circuits by reducing the subthreshold swing (SS) below the Boltzmann limit of 60 mV/dec. The basic idea is to replace the classical gate insulator with dielectrics that exhibit a negative capacitance (NC) associated with the double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. In this article, we demonstrate that the same NC effect can also be used to achieve the devices more robust to negative-bias temperature instability (NBTI), which continues to be a major reliability challenge for scaled p-type transistors. We demonstrate that with careful design of an NC-based Landau switch, the intrinsic NBTI degradation can be fully compensated while still maintaining hysteresis-free operation and steeper slope needed for the logic switch. In fact, the parasitic capacitances in a FinFET counterintuitively make a negative capacitance field effect transistor (NCFET) more NBTI tolerant. The proposed device is validated using the numerical simulations by technologically relevant p-type SiGe FinFeTs. The results suggest the intriguing possibility that a careful, physics-informed NCFET design can simultaneously achieve reliability performance metrics.

Comparative study on NBTI kinetics in Si p-FinFETs with B2H6-based and SiH4-based atomic layer deposition tungsten (ALD W) filling metal

A comparative study on negative bias temperature instability (NBTI) is carried out in replacement metal gate Si p-FinFETs featuring atomic layer deposition (ALD) tungsten (W) filling metal using B2H6 and SiH4 precursors. A fast measurement technique is used to characterize the threshold voltage shift (ΔVT). The effect of ALD W filling metal process on ΔVT, generated interface traps (ΔNIT), pre-existing hole traps (ΔNHT), stress voltage, and temperature dependence of degradation is demonstrated. Comparing with their B2H6-based counterpart, SiH4-based devices show reduced ΔVT under identical stress conditions due to reduced ΔNHT and ΔNIT. SiH4-based devices exhibit a 1.5 times higher fluorine content at the interfaces and larger compressive strain in the channel than B2H6-based devices, which are found to be responsible for the reduced ΔNIT. A modeling framework is proposed to model the long-term time evolution of NBTI degradation, and the predicted maximum overdrive voltage is compared. SiH4-based devices exhibit superior reliability and a 20% improvement in the maximum operation overdrive voltage than B2H6-based devices, and can be implemented in the advanced CMOS technology.

An Investigation of Field Reduction Effect on NBTI Parameter Characterization and Lifetime Prediction Using a Constant Field Stress Method

The impact of the field reduction effect on negative bias temperature instability (NBTI) parameter characterization and lifetime prediction was quantitatively studied in p-MOSFETs with a sub-1 nm equivalent oxide thickness (EOT). By comparing NBTI results under constant field stress and constant voltage stress, the field reduction effect was found to become severer at higher VG-STR and ${T}$ and cause a reduction in the voltage acceleration factor (VAF) at higher VG-STR and a reduction in activation energy EA at higher ${T}$ under constant voltage stress. To accurately evaluate NBTI lifetime, a modified NBTI model with field reduction correction (FRC) was proposed, and the 10-year NBTI degradation of a 32-stage ring oscillator was simulated. The results showed that the conventional model without including FRC had a worse prediction capability and overestimated frequency degradation for a ring oscillator. It is necessary to use an NBTI model with FRC for NBTI lifetime prediction of devices with a sub-1 nm EOT.

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.

Analysis of Negative Bias Temperature Instability Degradation in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors of Different Grain Sizes

This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.