Through silicon via (TSV) is commonly fabricated by high aspect ratio deep silicon etching, lining with dielectric layer for electrical isolation and super-conformal filing with copper. It has been reported that Cu-TSV can exert thermo-mechanical stress on Si due to coefficient of thermal expansion (CTE) mismatch. This stress can result in undesired device mobility variation and structural reliability. In addition, TSV parasitic capacitance has the most predominant impact on the circuit operation. It is therefore imperative to reduce the TSV stress and capacitance. One solution is to use low-k dielectric as the liner since it has much lower elastic modulus and effective permittivity. In this work, low-k dielectric is successfully integrated in TSV as a liner. The implications on TSV stress, capacitance and leakage current are discussed. Due to its smaller elastic modulus (~7.2 GPa), the selected low-k carbon-doped oxide acts as a compliant layer to cushion the Cu-TSV stress on the Si compared with conventional oxide (75 GPa) by plasma enhanced chemical vapor deposition. This effectively reduces the near-surface compressive stress in Si by >25% compared with the conventional liner which is more rigid. Since the low-k liner has an effective dielectric constant of ~2.8, it is found that the integration of the low-k liner reduces the TSV capacitance by ~26% as compared with the conventional oxide liner. In summary, this work has provided evidence of the technical merits of a low-k material to mitigate the undesired Cu-TSV induced stress in the surrounding Si and the related parasitic capacitance.
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