Near-interface Trap Research Articles

On the Origin of Threshold Voltage Instability under Operating Conditions of 4H-SiC n-Channel MOSFETs

We report on the threshold voltage () instability under operating conditions after gate bias switches at constant drain voltage for n-MOSFETs fabricated on 4H silicon carbide (4H-SiC). This effect occurs at room temperature and close to the of the device. We show that the origin of the instability is electron trapping into SiO2 over an energy barrier of (0.3-0.4) eV. These traps show similarities to traps previously observed in 4H-SiC MOS capacitors and labelled near interface traps (NITs). Further, the density of the traps can be reduced by one order of magnitude through post-oxidation annealing in nitric oxide atmosphere.

Investigation of Low-Frequency Noise Properties in High Mobility ZnON Thin-Film Transistors

We investigate the low-frequency noise (LFN) properties of amorphous zinc oxynitride (a-ZnON) thin-film transistors (TFTs) exhibiting high field-effect mobilities ranging from 48.5 to 118.9 cm2/ $\text {V}\cdot \text {s}$ , depending on the gas flow rates during the deposition process. The measured noise power spectral density of the drain current shows that the LFN in a-ZnON TFTs obeys the classical 1/ $f$ noise theory, i.e., it is proportional to 1/ $f^{\mathrm {\gamma }}$ with $\gamma \sim 1$ in the frequency range from 10 Hz to 1 kHz. The LFN from the a-ZnON TFT is successfully interpreted by the correlated number fluctuation-mobility fluctuation model. The near-interface dielectric trap density ( $N_{T})$ and the Coulomb scattering coefficient ( $\alpha _{S})$ extracted from the measured LFN in a-ZnON TFTs are similar to those from the previously reported values for amorphous indium–gallium–zinc oxide TFTs. The relatively large values of $N_{T}$ and $\alpha _{S}$ from the a-ZnON TFTs formed under O2-rich environment are mainly attributed to the high degree of disorder of the a-ZnON channel layer caused by the energetically broad and high density of subgap tail states.

Quantitative Characterization of Near-Interface Oxide Traps in 4H-SiC MOS Capacitors by Transient Capacitance Measurements

A method to characterize near-interface oxide trap density in SiC MOS capacitors using transient capacitance measurements was investigated, taking account of the distribution of de-trapping time of traps of various locations in oxide. The measurements at room and low temperatures enables us evaluate the responses of the raps of spatially deep and shallow locations, respectively. We found that the sample with low Dit showed smaller density of near-interface traps especially in spatially shallow region in the oxide.

Transient-Current Method for Measurement of Active Near-Interface Oxide Traps in 4H-SiC MOS Capacitors and MOSFETs

Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method.

Quantitative Characterization of Near-Interface Oxide Traps in 4H-SiC MOS Capacitors by Transient Capacitance Measurements

1．Introduction The characteristics of SiC MOS devices are often suffered from the effects of near-interface oxide traps, however, the quantitative analysis method of those traps has not been established. In this study we propose a method to estimate their density by transient capacitance measurement. We assume the oxide trap model [1], in which carriers in semiconductors interact with the traps in oxide by tunneling, with a widely-spread response time of the traps, due to the variation of the tunneling distance between the interface and the traps. 2. Characterization method Transient response of capacitance (C-t) gives the information of trapping behaviors of the carriers in MOS capacitors [2-3], since the change of amount of trapped charges shifts the C-V curve. In this study we employed the MOS capacitors fabricated by thermal oxidation of n-type 4H-SiC. The gate bias on a capacitor was kept in accumulation state (Vg=Vtrap) for 100 sec to fill the traps, before a sudden shift to flatband state (Vg=Vmeas) to observe the C-t characteristics. Taking account of widely-spread response time of the traps due to their depth distribution in oxide, the time-dependent change of capacitance would be described by extended-Debye relaxation model [4] instead of a conventional relaxation with a single time constant, as |C(t)-Ceq|≈|DC0|exp (-(t/τeff)β), where Ceq is the capacitance in thermal equilibrium, β is the stretched exponential factor (0<β<1) of response time, τeff is the effective relaxation time of the group of traps with distributed response time, and DC0 is the total change of capacitance. C-t characteristics at 200K and 300K were fitted by the above equation to determine DC0, from which the amount of trapped charges in near-interface traps per area (Qox ) was estimated by assuming that the distance of the traps from the interface is significantly shorter than the film thickness. Note that low temperature slows down the de-trapping process by a few orders because of the change of the Fermi-Dirac distribution. Even though our measurement system detects only relatively slow response (≥0.1 s), low temperature measurement enables us to evaluate the traps locating very shallow region(~ a few ongstroms from the interface). 3. Results and Discussions The observed C-t characteristics were well-fitted by the extended-Debye relaxation model as desribed above. The lower temperature measurements resulted in larger DC0 which is indicating more traps exist in the region closer to the interface. By changing the Vtrap while unchanging the Vmeas, we can vary the width of energy region of the traps contributing to the C-t characteristics. From the SiC surface potential dependence of Qox, we can deduce the effective density of states (Dox ) of the near-interface traps. We employed two kinds of MOS capacitors with different interface state density (Dit ): ~1012 cm-2eV-1 and ~1011 cm-2eV-1 at 0.2 eV below conduction band edge. For the near-interface oxide traps in shallow region (measured at 200K), we could detect Dox of 3-4×1012 cm-2eV-1 for the higher Dit sample, but only ~5×1011 cm-2eV-1 for the lower Dit sample. These traps are estimated to locate at a few angstroms distance from the interface, taking account of the tunneling mass of electrons in SiO2. On the other hand, both of the two samples showed relatively less density of traps for the deep region (measured at 300K), in the order of 1011 cm-2eV-1. The location of the traps detected at 300K is estimated to be ~ 1 nm depth from the interface. These results indicates that the oxide trap density in shallow region is significantly sensitive to the preparation condition of SiC/SiO2 interface. 4. Conclusions The method to determine the near-interface oxide trap density in MOS capacitors from transient capacitance characteristics was proposed and demonstrated for 4H-SiC MOS capacitors, by taking account of the wide distribution of distance between the traps and the interface. The effective state density of the near-interface traps was estimated to be 1011 ~1012 cm-2eV-1 for shallow location from the interface but ~1011 cm-2eV-1 for deep location for our MOS capacitors. 5. Acknowledgement This work was partly supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO), and by JSPS KAKENHI.

PECVD and Thermal Gate Oxides on 3C vs. 4H SiC: Impact on Leakage, Traps and Energy Offsets

Energy-band model offsets, trap density distributions and gate leakage characteristics of MOS capacitors with PECVD and thermal gate oxides on 3C-SiC and 4H-SiC were compared. The difference in trap energy distributions between the polytypes confirmed the lesser 3C-SiC polytype vulnerability to near-interface traps (NIT), which are alternatively found in high density in the 4H-SiC. It was also shown that the quality of the PECVD oxides obtained in this experiment were comparable to that of the thermal oxide. Only a slight increase of leakage current was observed in the PECVD oxides due to oxide inhomogeneity in the lower electric field interval of the Fowler-Nordheim range. Finally, the energy band model of the SiC MOS devices was described quantitatively for different combinations of polytype and oxidation method, which illustrated the influence of technological processing on the energy offsets and potentials, and could be used for further development of the devices and processes.

탄소나노튜브를 첨가한 4H-SiC MOS 캐패시터의 전기적 특성

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/<TEX>$SiO_2$</TEX> structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage (<TEX>$V_{FB}$</TEX>) shift was positive. Near-interface trap charge density (<TEX>$N_{it}$</TEX>) and negative oxide trap charge density (<TEX>$N_{ox}$</TEX>) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.

PECVD and Thermal Gate Oxides on 3C vs. 4H SiC – Impact on Leakage, Traps and Energy Offsets

Energy-band model offsets, trap density distributions and gate leakage characteristics of MOS capacitors with PECVD and thermal gate oxides on 3C- and 4H-SiC were compared. The difference in trap energy distributions between the polytypes demonstrated in this experiment confirms that the 3C-SiC polytype is less vulnerable to near-interface traps (NIT) which are found in high density in the 4H-SiC. It was also shown that the nitridation of SiO2 on SiC improves the leakage properties of the gate oxides. Finally, the energy band model of the SiC MOS devices was described quantitatively which could be considered in further development of the devices and processes.

PECVD and Thermal Gate Oxides on 3C Vs. 4H SiC – Impact on Traps, Leakage and Energy Offsets

Silicon carbide (SiC) is particularly suitable for manufacturing of medium and high power FETs. Two SiC polytypes most commonly used for that purpose, i.e. cubic 3C and hexagonal 4H, differ, however, in many aspects, which influence the operation of the devices. The differences in interface trap distributions, gate leakage and energy band model offsets resulting from the SiC polytypes were investigated in this work. Samples. Characterized were two lots of wafers (3C-SiC and 4H-SiC) fabricated by Acreo AB. The 3C-SiC lot consisted of two n-type (001) 3C-SiC wafers. The substrates from Hoya were covered at Acreo by a n-type epitaxial layer with nitrogen doping of 7×1015 cm-3. One wafer was thermally oxidized in wet oxygen (T = 1150°C, 1h) while the other had the SiO2 layer deposited by PECVD at T = 300°C. This second wafer was further annealed for 3 hours in wet oxygen at T = 950°C. The oxide thickness on both wafers was 60 nm.The 4H-SiC lot consisted of two SiC-4H n-type wafers, one with a thermal (53 nm) and another with a PECVD (45 nm) gate oxide fabricated in the processes analogical to the 3C-SiC lot. Measurements.The gate leakage currents were measured on Agilent B1500AB. The interface trap distributions were measured by standard conductance method on Agilent 4294A. The energy band model offsets were established using our own specialized equipment for photoelectric measurements. The methods used were discussed in details in [1,2,3]. Results. The important difference between the 3C and 4H polytypes is the width of the energy gap: EG(3C)=2.36 eV and EG(4H)=3.23 eV [4]. In Fig. 1 the trap density distributions measured in the samples in both polytypes are presented. The energy axis shows the trap distance from the top of the valence band EV, what enables the comparison of Dit in both systems. As expected, the Dit values in 4H-SiC are higher than those in 3C-SiC, irrespective of the oxide preparation method, due to the presence of a band of interface traps in the oxide, so called NIT (near-interface traps), caused probably by oxygen vacancy defects (O3ΞSiH HSiΞO3) producing trapping states at 3.0 eV...3.2 eV above EV, as reported by Afanas’ev [4] and others [5].An interesting feature can be demonstrated comparing gate leakage currents. In Fig. 2 we present the averaged leakage current density characteristics measured in both polytype samples. One can notice a very small difference in the leakage current density J between the oxides, while the difference with respect to the substrate polytype is very large. The density of leakage currents in 4H is by two orders of magnitude lower than that in 3C. Since the oxide preparation procedure in both samples was identical, the difference could not be explained by the oxide properties only. We presume that the mechanism of the increased leakage in the 3C-SiC is connected with trap enhanced tunneling from the conductance band by the NIT defects.Finally we present the most important 3C- and 4H-SiC MOSC energy-band model offsets shown in Fig. 3. The offset values are given in Tab. 1. All the values were taken for PECVD oxide and Al gate. Conclusions Energy-band model offsets, trap density distributions and gate leakage characteristics of MOS capacitors with PECVD and thermal gate oxide on 3C- and 4H-SiC were compared. The important role of NIT traps in both polytypes influencing different device characteristics was demonstrated.

Improved 4H-SiC metal oxide semiconductor interface produced by using an oxidized SiN gate oxide that had undergone post-oxidation annealing

We investigated oxidized SiN gate oxides that have undergone post-oxidation annealing (POA) treatment using diluted O2 (10% O2 in N2) at 1100 °C. The oxidized SiN/SiC interfaces were characterized by using capacitance-voltage (C-V) measurements, Auger electron spectroscopy (AES), high-resolution transmission electron microscopy (HR-TEM), and X-ray photoelectron spectroscopy (XPS). POA for 60 min significantly improved the interface trap density (D it ), near-interface trap density (N it ), and effective oxide charge density (Q eff ) of the oxidized SiN. However, improvement was not observed for the as-oxidized SiN sample or the oxidized SiN sample that had undergone POA for 120 min. The electrical properties of metal-oxide semiconductor devices fabricated using these oxides are discussed in terms of the oxide chemical composition.

Growth of Gate Oxides on 4H-SiC by NO at Low Partial Pressures

In an attempt to significantly reduce the amount of nitric oxide (NO), commonly used to improve the quality of gate oxides on 4H–SiC, a series of alternative gate oxidation processes using a combination of O2 and NO gas mixtures at low partial pressures were investigated. The properties of 4H–SiC/SiO2 interfaces on n-type MOS capacitors were examined by the measurement of accumulation conductances over a range of frequencies. Oxide integrity was evaluated by current–voltage measurements and by the extraction of the conduction band offset barrier heights through Fowler–Nordheim (F–N) analysis. A notable reduction of accumulation conductance, indicating a reduction of near-interface traps (NITs), was observed over all measured frequencies for oxidation processes containing NO with a partial-pressure of only 2%. Gate oxides grown in mixture of O2 and NO at low-partial-pressures demonstrated a considerable improvement of dielectric properties, increasing the barrier height to near theoretical values.

Theory of near-interface trap quenching by impurities in SiC-based metal-oxide-semiconductor devices

Oxidizing SiC in the presence of various impurities (e.g., sodium, potassium, nitrogen, and phosphorous) has been previously observed to result in a significant reduction of the electron traps in the gate oxide near the SiC-SiO2 interface. Here, we explore the electro-chemistry of the impurity elements involved using first-principles quantum mechanical calculations. Our results indicate that the observed reduction in the near interface traps (NITs) is not due to direct chemical passivation. Instead, we show that the quenching occurs because the NIT energy levels are lowered by the Coulombic tail of the positively charged impurities and thus become inaccessible to the experimental measurements. This new proposal explains a variety of experiments and leads to specific predictions.

Verification of Near-Interface Traps Models by Electrical Measurements on 4H-SiC n-Channel Mosfets

4H-SiC n-channel lateral MOSFETs were manufactured and characterized electrically by current-voltage measurements and by numerical simulation. To describe the observed electrical characteristics of the SiC MOSFETs, Near-Interface Traps (NIT) and mobility degradation models were included in the simulation. The main finding of the simulation is that two models for the NIT states in the upper part of the SiC bandgap are able to describe the electrical data equally well. In one of them, acceptor-like traps and fixed charge are considered while in a newly developed one, donor-like traps are taken into account also.

DLTS Evaluation of Near-Interface Traps in Ge-MIS Structures Fabricated by ECR-Plasma Techniques

A Ge-MIS structure has attracted attention for the candidate of a next generation CMOS device. To date, we have successfully developed Ge-MIS structures with superior interface qualities by ECR (Electron Cyclotron Resonance) plasma techniques. In addition, we have shown that DLTS (Deep Level Transient Spectroscopy) method is useful for evaluating the Ge-MIS structures. In this report, we have evaluated the near-interface traps in GeNx/Ge structures by DLTS method, and have evaluated the effect of annealing on reducing the traps. The traps observed in the Ge-MIS samples were greatly reduced by 400°C annealing. The origins of the traps are also discussed by comparing with the traps in germanium reported to date.

The Influence of Gate Material, SiO&lt;sub&gt;2&lt;/sub&gt; Fabrication Method and Gate Edge Effect on Interface Trap Density in 3C-SiC MOS Capacitors

This paper reports on results of interface trap analysis of 3C-SiC MOS capacitors fabricated using four different gate materials and two SiO2 oxide preparation methods. The results indicate that post-deposition annealing in wet oxygen of PECVD deposited SiO2 samples increases the near-interface or slow trap densities, compared with wet oxygen thermally oxidized samples. It has also been found that the energy distribution, Dit, of electron states at the oxide/SiC interface of MOS capacitors with different sizes depend on the factor R=P/A, where P stands for the gate perimeter and A for the gate area, which is related to the amount of stress under the edge of the metallic gate.

Instability of 4H-SiC MOSFET Characteristics due to Interface Traps with Long Time Constants

Instability of metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics was evaluated by DC and pulse current-voltage (I-V) measurements. MOSFETs with nirided gate oxides were fabricated on C-face 4H-SiC. Their interfaces have near interface traps (NITs) with long time constants, depending on the cooling down process after nitridation. Such devices exhibited a large hysteresis in DC I-V and a large transient current in pulse I-V measurements. These phenomena can be explained by the charge state of NITs due to capture/emission of electrons in the channel.

Reduction in the Density of Interface States at the SiO&lt;sub&gt;2&lt;/sub&gt;/4H-SiC Interface after Dry Oxidation in the Presence of Potassium

We report a strong reduction in the density of near-interface traps (NITs) at the SiO2/4H-SiC interface after dry oxidation in the presence of potassium. This is accompanied by a significant enhancement of the oxidation rate. The results are in line with recent investigations of the effect of sodium on oxidation of 4H-SiC. It is evident that both alkali metals enhance the oxidation rate of SiC and strongly influence the energy distribution of interface states.

Analysis of trap effect on reliability using the charge pumping technology in La-incorporated high-k dielectrics

In this paper, reliability characteristics of nMOSFETs with La-incorporated HfSiON and HfON and metal gate have been studied. HfLaSiON shows greater device degradation by hot carrier (HC) stress than by positive bias temperature (PBT) stress, while HfLaON exhibits similar degradation during HC stress and PBT stress. To evaluate the contribution of bulk trap during PBT stress, a novel charge pumping (CP) technique is applied to extract the distribution of bulk trap (N bt) before and after PBT stress. To evaluate permanent damage during HC stress, an appropriate selection of frequency range in CP method is considered. The initial interface trap density of HfLaSiON and HfLaON is similar, while the near-interface trap (N IT) density of HfLaSiON after HC stress is equal or greater than that of HfLaON.

Removal of near-interface traps at SiO2/4H–SiC (0001) interfaces by phosphorus incorporation

Effective removal of near-interface traps (NITs) in SiO2/4H–SiC (0001) structures through phosphorus incorporation is demonstrated in this paper. Low-temperature capacitance-voltage and thermal dielectric relaxation current measurements were employed to investigate NITs in oxides prepared by dry oxidation, NO annealing, and POCl3 annealing. Both the measurements revealed that the density of electrons trapped in NITs in POCl3-annealed oxide is smaller than that in dry and NO-annealed oxides. The drastic elimination of NITs lowers the interface state density and increases the channel mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors.

Detection and Electrical Characterization of Defects at the SiO&lt;sub&gt;2&lt;/sub&gt;/4H-SiC Interface

Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (ECEit &gt; 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.