Nanowire Transistors Research Articles

Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement

In this work, we propose an analytical model for the intrinsic transcapacitances in ultra-thin gate-all-around junctionless nanowire field effect transistors in the presence of confined energy states of electrons. The validity of the developed model is confirmed from deep depletion to accumulation and from linear to saturation, based on the numerical solution of the Schrödinger equation using Technology Computer Aided Design (TCAD) simulations. This represents an important stage toward AC small signal analysis of junctionless nanowire-based circuits.

Performance of vertical gate-all-around nanowire p-MOS transistors determined by boron depletion during oxidation

Vertical junctionless gate-all-around nanowire transistors show excellent electrical performance and can be fabricated using a top-down approach in conventional CMOS process technology. Thinning of the nanowires to the desired diameter is obtained by sacrificial wet oxidation. Then, the gate oxide is grown by dry oxidation. These oxidation steps deeply affect the doping distribution in the nanowire due to dopant segregation and self-interstitial injection, especially for p-type dopants. This effect is more pronounced in 3D nanostructures with respect to bulk devices, due to geometry. Modeling the resulting doping distribution is a prerequisite for understanding the electrical properties of the devices and exploring their potential for optimization. In this work, 3D TCAD process and device simulations were performed using Synopsys Sentaurus and the results are compared with experimental data of devices fabricated at CNRS-LAAS. The impact of the implemented process and device models and their capability to predict nanowire properties and device behavior is assessed.

Synaptic devices based on gate-all-around InAs nanowire field effect transistor

In this paper, we proposed a gate-all-around InAs nanowire field effect transistor (GAA InAs NW FET) that can simulate synaptic behaviors such as short-term potentiation (STP) and long-term potentiation (LTP). The native oxide layer (In2O3) on the surface of InAs NW serves as a charge trapping layer for storing information. The transition from short-term potentiation (STP) to long-term potentiation (LTP) can be achieved by properly adjusting the gate voltage. Due to enhanced gate controllability, the GAA InAs NW FETs are expected to be widely used and promising in neuromorphic systems and networks.

(Digital Presentation) Nanowire Transistors with Bound‐Charge Engineering

Low-dimensional electronic systems such as silicon nanowires exhibit weak screening which is detrimental to the performance and scalability of nanodevices, e.g., tunnel field-effect transistors. By atomistic quantum transport simulations, we show how bound charges can be engineered at interfaces of Si and low-κ oxides to strengthen screening. To avoid compromising gate control, low-κ and high-κ oxides areused in conjunction. In Si nanowire tunnel field-effect transistors, we demonstrate that bound charge engineering increases the on-state current by orders of magnitude, and the combination of oxides yields minimal subthreshold swing. Finally, an analytical model is developed for Si nanowire FET assisted by bound charge engineering. We conclude that the proposed bound-charge engineering paves a way toward improved low-power transistors.

A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.35\times $ </tex-math></inline-formula> power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications.

Transport spectroscopy from Hubbard bands of dopant-induced quantum dot array to one-dimensional conduction subband

Arrays of dopant-induced quantum dots (QDs) are promising candidates as quantum bit platforms. We have achieved quantum transport spectroscopy of a junctionless silicon (Si) nanowire transistor with dual physical channels with a diameter of 10 nm fabricated by novel femtosecond laser projection exposure together with thermal oxidation. The spectroscopy demonstrates the evolution of the quantum transport process from Hubbard bands of dopant-induced QD array to one-dimensional (1D) conduction subbands. Eight pairs of current splitting peaks were observed at the initial stage of the drain current, representing the upper and lower Hubbard bands formed by the coupling of eight QDs. The current oscillation peaks in the 1D conduction subband elucidate the interference of reflected electron waves between the gate-defined barriers, which are proved by the mean wave vector interval matching the gate length. Our experimental results demonstrate the evolution of the quantum transport process in sub 10 nm dual Si channels with randomly doped dopant atoms, opening a new perspective for quantum states by dopant band engineering in Si nanoscale devices for scalable quantum computation.

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.

Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling

In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity (ρC) values are 1.6 × 10−5 Ω cm2 (Mo) and 4.2 × 10−6 Ω cm2 (Pd) for a doping level of 1 × 1019 cm−3. An apparent dependence of ρC on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used.

Random telegraph signals in nanoscale vertical junctionless transistors with gate-all-around

The role of a single defect on the performance of transistors must be better understood to improve the design and fabrication process of nanotransistors. Capacitive networks on 18 nm long gate junctionless (JL) vertical gate-all-around nanowire transistors are studied through random telegraph signals, with amplitudes as high as 60% for a single nanowire. Defect densities extracted from both JL and accumulation-mode transistors allows one to discuss number fluctuation-based noise models, questioning the significance of defect densities of less than one defect per nanodevice. It is shown that the consideration of an effective charge in the models solves this issue.

An Enhanced Statistical Phonon Transport Model for Nanoscale Thermal Transport

Abstract Silicon nanowire transistors are thought to be ideal transistor devices due to electrostatic control of the gate, and the International Roadmap for Devices and Systems has indicated that arrays of these devices are possible for future transistor devices. Nonequilibrium phonon transport due to self-heating in silicon nanowire transistors affects performance in the areas of carrier mobility, speed, aging, and thermal failure. Existing methods for phonon transport modeling range in fidelity and flexibility. Direct quantum or atomic simulations offer high fidelity with reduced flexibility while Monte Carlo methods offer enhanced flexibility for reduced fidelity. An enhanced statistical phonon transport model (enhanced SPTM) is presented to fill the gap between Monte Carlo and direct atomic methods. Application of the enhanced SPTM to one-dimensional (1D) simulations of silicon nanowire devices illustrates production of design relative information. Simulation results indicated an excess build-up of up to 14% optical phonons beyond equilibrium values giving rise to transient local temperature hot spots of 60 Kelvin in the drain region. The local build-up of excess optical phonons in the drain region has implications on performance and reliability.The enhanced SPTM is a valid engineering design tool for evaluating the thermal performance of silicon nanowire transistor designs. The phonon fidelity of the enhanced SPTM is greater than Monte Carlo and the Boltzmann Transport Equation and the length-scale and time-scale fidelity of the enhanced SPTM is better than direct atomic simulation.

Design and Fabrication of Electrostatically Formed Nanowire Gas Sensors With Integrated Heaters

This work reports on the design and fabrication of planar gas sensors with membrane structure to allow in-situ heating capabilities crucial for enhancing gas sensing performances. The sensors are virtual nanowire field-effect transistor (FET) type devices, referred to as electrostatically formed nanowire (EFN) sensors. This work describes the design, fabrication, and performance of a 2 mm X 2 mm chip with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$850 ~\mu \text{m}$ </tex-math></inline-formula> diameter, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.5 ~\mu \text{m}$ </tex-math></inline-formula> thick membrane. The design has been analyzed using finite element simulations (FEM) and verified experimentally. The thermal efficiency of the heated membrane is found to be 10 mW to reach 400 °C, which is better than most of the reported membrane-based sensors. To improve sensitivity and for broader functionality, the sensing surface, unlike reported in most designs, is at the bottom of the membrane. The technology allows system on chip (SoC) integration and further can be used for the fabrication of handheld battery-operated gas detectors. [2021-0248]

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node.

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.

Investigation of the cross-sectional morphology of epitaxial Si nanowires grown by chemical vapor deposition for the fabrication of vertical devices

The interfacial structure of Si nanowire transistors is decisively important to their electronic properties. Smooth sidewall surface of Si nanowires is therefore a prerequisite for the fabrication of vertical transistors. In this study, the axial cross-sectional morphology of epitaxial Si nanowires, which are grown vertically on Si[111] substrates by chemical vapor deposition via the vapour-liquid-solid mechanism, are analyzed by transmission electron microscopy to understand their surface morphology. It is noted that the cross-sections do not exhibit sharp facets. The roughness of the sidewall surface is attributed to precipitation of Si from AuSi liquid droplets. The cross-sectional shape of the Si nanowires is truncated-triangular, but not exactly symmetric. A larger distortion of the cross-sectional shape appears in tilted nanowires. It is also demonstrated that after removing the surface Au, post-growth oxidation of Si nanowires is helpful to rebuild smooth sidewall surface.

Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor

We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO2 interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 1012 cm–2 and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.

Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic small-signal parameters such as the gate capacitances.

Simulation and Comparison of Current-Voltage Characteristics in Double Gate Nanowire FET Using ZnO and SiO2 as Gate Oxide Materials

The aim of the project is to simulate and compare current-voltage characteristics in double gate nanowire field effect transistors made of ZnO and SiO2 gate oxides with thicknesses ranging from 1 to 30 nm. Materials and methods: The drain characteristics of double gate nanowire FET for the two gate oxides were considered for analysis. Altogether 147 drain current samples were considered for each group. Results: The two groups are subjected to an independent sample test using SPSS software, which calculates the significant mean value. The SPSS tool's chart builder is used to create a statistical graph. The mean for those in the highest quartile of drain current of ZnO based DG NW FET (drain current=0.461 mA, 95% CI:0.232-0.458 mA, p&lt;0.05), but in SiO2 based DG NW FET (drain current=0.115 mA, 95% CI:0.232-0.458 mA, p&lt;0.05). Conclusion: ZnO nanowire field-effect transistors have better switching characteristics and higher drain current than SiO2. The drain current is altered by varying the oxide thickness of the material. The drain current of ZnO is significantly higher than that of SiO2.

Interface traps density extraction through transient measurements in junctionless transistors

This paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.

Design of New Ternary Inverter Gate Based on the Nanowire Transistor

Design of New Ternary Inverter Gate Based on the Nanowire Transistor

Analysis of Electric Field Distribution for SOI-FET Sensors with Dielectrophoretic Control.

Silicon-on-insulator (SOI) nanowire or nanoribbon field-effect transistor (FET) biosensors are versatile platforms of electronic detectors for the real-time, label-free, and highly sensitive detection of a wide range of bioparticles. At a low analyte concentration in samples, the target particle diffusion transport to sensor elements is one of the main limitations in their detection. The dielectrophoretic (DEP) manipulation of bioparticles is one of the most successful techniques to overcome this limitation. In this study, TCAD modeling was used to analyze the distribution of the gradient of the electric fields E for the SOI-FET sensors with embedded DEP electrodes to optimize the conditions of the dielectrophoretic delivery of the analyte. Cases with asymmetrical and symmetrical rectangular electrodes with different heights, widths, and distances to the sensor, and with different sensor operation modes were considered. The results showed that the grad E2 factor, which determines the DEP force and affects the bioparticle movement, strongly depended on the position of the DEP electrodes and the sensor operation point. The sensor operation point allows one to change the bioparticle movement direction and, as a result, change the efficiency of the delivery of the target particles to the sensor.

Extended-SWIR Photodetection in All-Group IV Core/Shell Nanowires

Group IV Ge1-xSnx semiconductors hold the premise of enabling broadband silicon-integrated infrared optoelectronics due to their tunable bandgap energy and directness. Herein, we exploit these attributes along with the enhanced lattice strain relaxation in Ge/Ge0.92Sn0.08 core-shell nanowire heterostructures to implement highly responsive, room-temperature short-wave infrared nanoscale photodetectors. Atomic-level studies confirm the uniform shell composition and its higher crystallinity with respect to thin films counterparts. The demonstrated Ge/Ge0.92Sn0.08 p-type field-effect nanowire transistors exhibit superior optoelectronic properties achieving simultaneously a relatively high mobility, a high ON/OFF ratio, and a high responsivity, in addition to a broadband absorption in the short-wave infrared range. Indeed, the reduced bandgap of the Ge0.92Sn0.08 shell yields an extended cutoff wavelength of 2.1 um, with a room-temperature responsivity reaching 2.7 A/W at 1550 nm. These results highlight the potential of Ge/Ge1-xSnx core/shell nanowires as silicon-compatible building blocks for nanoscale integrated infrared photonics.