Nordic researchers unveil their novel InAs/InGaAs nanowire MOSFETs on Si, which exhibit high-frequency gains for use in a gate-last configuration. The architecture of the device enables highly asymmetric capacitances, increasing its power gain. The authors' device shows a transit frequency (fT) of 120 GHz and maximum frequency (fmax) of 130 GHz, from a channel length (Lg) of 120 nm, demonstrating the state-of-the-art performance of their architecture. Moore's law states that the number of transistors on a microchip doubles roughly every 2 years, and has been the driving force behind the development of electrical devices for the past few decades. Silicon-based metal-oxide semiconductor field effect transitors (MOSFETs) in particular have become a rapidly developing area of research due to their high degree of scalability in digital applications. MOSFETs combining group 3 and group 5 elements (so called ‘III-V’ MOSFETs) in particular have performed beyond other transistor architectures in the realms of transconductance and the on-current. Difference between gate-last and gate-first fabrications SEM picture after gate-finger fabrication For higher frequency transistors, the inability to scale high-electron-mobility transistors (HEMTs) due to an insufficient gate-barrier has caused development of fT to stagnate around 700 GHz. The authors propose that better scaling in III-V MOSFETs could hold the key to surpassing HEMTs in high-frequency applications. Indeed, it has been shown that a number of planar MOSFETs recently have displayed fT values in the region of 400 GHz. The authors in their publication in Electronics Letters present the prospect of verical III-V nanowires for use in high-frequency devices. The nanowires are grown using a technique known as VLS, or ‘vapor-liquid-solid’ growth. This scheme is more easily integrated on a Silicon substrate, and also allows engineering of the band-gap properties of the semiconductor, giving rise to improved intrinsic voltage gain and a higher breakdown voltage without the deterioration of other performance metrics. The growth of vertical nanowire MOSFETs can be generally divided into two processes: gate-last and gate-first processes. Gate-first processes are generally less desirable, as they produce thin nanowire contacts and leave ungated regions at the top of the nanowire, which increases the access resistance at this point. Gate-last devices form a recessed gate and add metal to the sidewalls of the nanowire, reducing the access resistance. The gate-last MOSFETs produced by the authors here are based on InAs/In0.4Ga0.6As heterostructure nanowires which have been fabricated on a Si{111} substrate. The wire can be considered in 3 parts: a bottom segment made of highly-doped InAs, a middle segment which is unintentionally doped as the wire transitions from InAs to InGaAs and a top segment which is highly doped InGaAs. The middle and bottom segments are each 100 nm in length, whilst the top segment measures 300 nm in length. The gate connects the bottom and middle segments. The authors provide a comparison with a number of other MOSFET devices produced on Silicon. Their device shows comparable performance with the referenced works, even before the full optimisation of their device. Such optimisations will take the form of further scaling of the structure to reduce capacitances. Authors note that their device should be scalable all the way down to 25 nm. The work presented in Electronics Letters could prove to be a key piece of the puzzle when dealing with the continued minimisation of electronic circuits, with early results showing that the proposed architecture is capable of keeping up with current state-of-the-art devices.
Read full abstract