Nanoscale Memristor Research Articles

A Native Stochastic Computing Architecture Enabled by Memristors

A two-terminal memristor device is a promising digital memory for its high integration density, substantially lower energy consumption compared to CMOS, and scalability below 10 nm. However, a nanoscale memristor is an inherently stochastic device, and extra energy and latency are required to make a deterministic memory based on memristors. Instead of enforcing deterministic storage, we take advantage of the nondeterministic memory for native stochastic computing, where the randomness required by stochastic computing is intrinsic to the devices without resorting to expensive stochastic number generation. This native stochastic computing system can be implemented as a hybrid integration of memristor memory and simple CMOS stochastic computing circuits. We use an approach called group write to program memristor memory cells in arrays to generate random bit streams for stochastic computing. Three methods are proposed to program memristors using stochastic bit streams and compensate for the nonlinear memristor write function: voltage predistortion, parallel single-pulse write, and downscaled write and upscaled read. To evaluate these technical approaches, we show by simulation a memristor-based stochastic processor for gradient descent optimization, and k-means clustering. The native stochastic computing based on memristors demonstrates key advantages in energy and speed in compute-intensive, data-intensive, and probabilistic applications.

Influence of the cross section area on the conductive characteristics of titanium oxide memristor

The conduction of nano-scale titanium oxide memristor exhibits complex characteristics, owing to the change of self-parameters and the coexistence of different conductive mechanisms. However, there has been no detailed discussion about the influence of the cross section area change on the conductive characteristics of memristor. Based on dopant drift and tunnel barrier mechanisms, the conductive process of memristor is analysed, and the relevance between cross section area and key physical factors of the conductive process is studied, then the influences of the changes of titanium oxide and tunnel barrier cross section area on conductive characteristics of memristors are studied, respectively. The differences and connections between the two cases are analysed. In the case of the coexistence of those two mechanisms, compared with the change of titanium oxide cross section area, the change of tunnel barrier cross section area is proved to be the chief factor which causes changes of memristor conductive characteristics, it is also a possible factor causing the change of non-ideal conductive characteristics of memristor. The research results contribute to further explaining the complexity of memristor conductions and providing basis for optimizing memristor modeling.

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

A scalable neural chip with synaptic electronics using CMOS integrated memristors

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Integration of nanoscale memristor synapses in neuromorphic computing architectures

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

The conductive mechanisms of a titanium oxide memristor with dopant drift and a tunnel barrier

Nano-scale titanium oxide memristors exhibit complex conductive characteristics, which have already been proved by existing research. One possible reason for this is that more than one mechanism exists, and together they codetermine the conductive behaviors of the memristor. In this paper, we first analyze the theoretical base and conductive process of a memristor, and then propose a compatible circuit model to discuss and simulate the coexistence of the dopant drift and tunnel barrier-based mechanisms. Simulation results are given and compared with the published experimental data to prove the possibility of the coexistence. This work provides a practical model and some suggestions for studying the conductive mechanisms of memristors.

Synaptic behavior and STDP of asymmetric nanoscale memristors in biohybrid systems

We fabricate and characterize asymmetric memristors which show a very strong single-sided hysteresis. When biased in one direction there is hysteresis and in the opposite direction there is a lack of hysteresis. We demonstrate that this apparent lack is actually hysteresis on a much faster time-scale. We further demonstrate that this form of asymmetric behavior correlates very well to the asymmetric structure and function of an actual synapse. The asymmetric memristor device presented here is necessary to correctly implement spike-timing-dependent-plasticity STDP in mixed memristor/neuron hybrid systems as an artificial synapse. These devices show the required characteristics for implementing the asymmetric form of long-term potentiation (LTP) and long-term depression (LTD) of a synapse between two neurons, where symmetric memristor devices do not. Signals from a presynaptic neuron are sent via its axon across the synapse to the dendrite of a postsynaptic neuron. Postsynaptic neuron signals sent to subsequent neurons have an influence on the strength of any further presynaptic neuron signals received by the postsynaptic neuron across the synapse. These signals are grouped into spike triplets within the framework of STDP and, as we experimentally show here, can be implemented with asymmetric memristors, not standard symmetric memristors.

A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems

Recent research in nanotechnology has led to the practical realization of nanoscale devices that behave as memristors, a device that was postulated in the seventies by Chua based on circuit theoretical reasonings. On the other hand, neuromorphic engineering, a discipline that implements physical artifacts based on neuroscience knowledge, has related neural learning mechanisms to the operation of memristors. As a result, neuro-inspired learning architectures can be proposed that exploit nanoscale memristors for building very large scale systems with very dense synaptic-like memory elements. At present, the deep understanding of the internal mechanisms governing memristor operation is still an open issue, and the practical realization of very large scale and reliable ?memristive fabric? for neural learning applications is not a reality yet. However, in the meantime, researchers are proposing and analyzing potential circuit architectures that would combine a standard CMOS substrate with a memristive nanoscale fabric on top to realize hybrid memristor-CMOS neural learning systems. The focus of this paper is on one such architecture for implementing the very well established Spike-Timing-Dependent-Plasticity (STDP) learning mechanism found in biology. In this paper we quickly review spiking neural systems, STDP learning, and memristors, and propose a hybrid memristor-CMOS system architecture with the potential of implementing a large scale STDP learning spiking neural system. Such architecture would eventually allow to implement real-time brain-like processing learning systems with about neurons and synapses on one single Printed Circuit Board (PCB).

The memory effect of nanoscale memristors investigated by conducting scanning probe microscopy methods

We report on the use of scanning force microscopy as a versatile tool for the electrical characterization of nanoscale memristors fabricated on ultrathin La0.7Sr0.3MnO3 (LSMO) films. Combining conventional conductive imaging and nanoscale lithography, reversible switching between low-resistive (ON) and high-resistive (OFF) states was locally achieved by applying voltages within the range of a few volts. Retention times of several months were tested for both ON and OFF states. Spectroscopy modes were used to investigate the I–V characteristics of the different resistive states. This permitted the correlation of device rectification (reset) with the voltage employed to induce each particular state. Analytical simulations by using a nonlinear dopant drift within a memristor device explain the experimental I–V bipolar cycles.

A Novel Chaotic Neural Network Using Memristive Synapse with Applications in Associative Memory

Chaotic Neural Network, also denoted by the acronym CNN, has rich dynamical behaviors that can be harnessed in promising engineering applications. However, due to its complex synapse learning rules and network structure, it is difficult to update its synaptic weights quickly and implement its large scale physical circuit. This paper addresses an implementation scheme of a novel CNN with memristive neural synapses that may provide a feasible solution for further development of CNN. Memristor, widely known as the fourth fundamental circuit element, was theoretically predicted by Chua in 1971 and has been developed in 2008 by the researchers in Hewlett‐Packard Laboratory. Memristor based hybrid nanoscale CMOS technology is expected to revolutionize the digital and neuromorphic computation. The proposed memristive CNN has four significant features: (1) nanoscale memristors can simplify the synaptic circuit greatly and enable the synaptic weights update easily; (2) it can separate stored patterns from superimposed input; (3) it can deal with one‐to‐many associative memory; (4) it can deal with many‐to‐many associative memory. Simulation results are provided to illustrate the effectiveness of the proposed scheme.

Short-Term Memory to Long-Term Memory Transition in a Nanoscale Memristor

"Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories.

Nanoscale Memristor Device as Synapse in Neuromorphic Systems

A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal-oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.