Nanoscale Circuits Research Articles

Single InxGa1−xAs nanowire/p-Si heterojunction based nano-rectifier diode

Nanoscale power supply units will be indispensable for fabricating next generation smart nanoelectronic integrated circuits. Fabrication of nanoscale rectifier circuits on a Si platform is required for integrating nanoelectronic devices with on-chip power supply units. In the present study, a nanorectifier diode based on a single standalone InxGa1−xAs nanowire/p-Si (111) heterojunction fabricated by metal organic chemical vapor deposition technique has been studied. The nanoheterojunction diodes have shown good rectification and fast switching characteristics. The rectification characteristics of the nanoheterojunction have been demonstrated by different standard waveforms of sinusoidal, square, sawtooth and triangular for two different frequencies of 1 and 0.1 Hz. Reverse recovery time of around 150 ms has been observed in all wave response. A half wave rectifier circuit with a simple capacitor filter has been assembled with this nanoheterojunction diode which provides 12% output efficiency. The transport of carriers through the heterojunction is investigated. The interface states density of the nanoheterojunction has also been determined. Occurrence of output waveforms incommensurate with the input is attributed to higher series resistance of the diode which is further explained considering the dimension of p-side and n-side of the junction. The sudden change of ideality factor after 1.7 V bias is attributed to recombination through interface states in space charge region. Low interface states density as well as high rectification ratio makes this heterojunction diode a promising candidate for future nanoscale electronics.

Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology

This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications. Nanoscale circuits are more susceptible to transient faults or soft errors due to the reduction of the stored charge in their sensitive nodes. Hereupon, low-cost and tolerant circuits design is a significant challenge, especially in the nanoscale storage cells. In addition, the proposed ST is utilized for designing a low-power hardened latch. In the proposed design, instead of up-sizing and increasing the input capacitance, the determined hysteresis mechanism of the proposed ST buffer is utilized to improve the single event upset hardness. The simulations are conducted based on the Stanford CNTFET model at 16-nm technology node. According to the results, the proposed ST has on average 90% lower power-delay product and higher robustness to PVT variations as compared to its most efficient CNTFET-based counterparts. Moreover, the simulations confirm the considerable tolerance of the proposed hardened latch to the multiple node upset as compared to the state-of-the-art designs. The proposed hardened latch has on average 68% higher critical charge, which considerably enhances its reliability and on average 16% smaller area as compared to its counterparts.

Thermal conductance of Nb thin films at sub-kelvin temperatures

We determine the thermal conductance of thin niobium (Nb) wires on a silica substrate in the temperature range of 0.1–0.6 K using electron thermometry based on normal metal-insulator-superconductor tunnel junctions. We find that at 0.6 K, the thermal conductance of Nb is two orders of magnitude lower than that of Al in the superconducting state, and two orders of magnitude below the Wiedemann-Franz conductance calculated with the normal state resistance of the wire. The measured thermal conductance exceeds the prediction of the Bardeen-Cooper-Schrieffer theory, and demonstrates a power law dependence on temperature as T4.5, instead of an exponential one. At the same time, we monitor the temperature profile of the substrate along the Nb wire to observe possible overheating of the phonon bath. We show that Nb can be successfully used for thermal insulation in a nanoscale circuit while simultaneously providing an electrical connection.

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, $$I_{\mathrm{on}} /I_{\mathrm{off}}$$Ion/Ioff ratio, transconductance, unity-gain frequency ($$f_{\mathrm{T}}$$fT), maximum oscillation frequency ($$f_{\mathrm{max}}$$fmax) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.

Optical metasurfaces for subwavelength difference operations

Coupled metal nanostructures supporting localized surface plasmon resonances are represented as a nanoscale optical circuit that takes light fields as inputs and forms linear combinations of them with complex coefficients. The subwavelength arrays of these circuits form a metasurface that performs mathematical operations in two dimension on an incident light field. We demonstrate this concept with subwavelength scale plasmonic circuits that perform difference operations. The metasurface is fabricated from the arrays of coupled gold nanorods where each group of three rods forms the difference circuit. The operation of the metasurface is demonstrated experimentally.

Toehold-Mediated Displacement of an Adenosine-Binding Aptamer from a DNA Duplex by its Ligand.

DNA is increasingly used to engineer dynamic nanoscale circuits, structures, and motors, many of which rely on DNA strand-displacement reactions. The use of functional DNA sequences (e.g., aptamers, which bind to a wide range of ligands) in these reactions would potentially confer responsiveness on such devices, and integrate DNA computation with highly varied molecular stimuli. By using high-throughput single-molecule FRET methods, we compared the kinetics of a putative aptamer-ligand and aptamer-complement strand-displacement reaction. We found that the ligands actively disrupted the DNA duplex in the presence of a DNA toehold in a similar manner to complementary DNA, with kinetic details specific to the aptamer structure, thus suggesting that the DNA strand-displacement concept can be extended to functional DNA-ligand systems.

Toehold‐Mediated Displacement of an Adenosine‐Binding Aptamer from a DNA Duplex by its Ligand

AbstractDNA is increasingly used to engineer dynamic nanoscale circuits, structures, and motors, many of which rely on DNA strand‐displacement reactions. The use of functional DNA sequences (e.g., aptamers, which bind to a wide range of ligands) in these reactions would potentially confer responsiveness on such devices, and integrate DNA computation with highly varied molecular stimuli. By using high‐throughput single‐molecule FRET methods, we compared the kinetics of a putative aptamer–ligand and aptamer–complement strand‐displacement reaction. We found that the ligands actively disrupted the DNA duplex in the presence of a DNA toehold in a similar manner to complementary DNA, with kinetic details specific to the aptamer structure, thus suggesting that the DNA strand‐displacement concept can be extended to functional DNA–ligand systems.

Statistical soft error rate estimation of combinational circuits using Bayesian networks

Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters

Majority voters are typically used in redundancy hardening techniques aiming to increase the reliability of nanoscale circuits. Besides, Spin Transfer Torque Magnetic Tunnel Junction (STT-MJT) has been identified as the most promising candidate for low power and high speed applications. In this paper, we present two majority voter circuits based on nanometer STT-MTJ. By using STMicroelectronics FDSOI 28nm process and a precise STT-MTJ compact model, electrical simulations have been carried out to compare their performances and analyze their reliability. Both radiation sensitivity and variability have been investigated in the reliability-aware analysis.

An optimal design of full adder based on 5-input majority gate in coplanar quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is one of the alternative technologies that enable nanoscale circuit design with high performance and low power consumption features. In this aspect, QCA wire crossing is a challenging task in the coplanar QCA fabrication, as defects appear to be inherent due to two cell types in single layout structure. This work showcases an extensive structural and power analysis of previous 5-input majority gates. It has been found that the existing 5-input majority gates are not power efficient and the structures are not well optimized. To overcome this, we have proposed a new low-complexity coplanar 5-input majority gate, which consumes less power compared to prior designs. To evaluate the usefulness of proposed gate a new one bit full adder circuit is presented. The proposed full adder is more robust and enjoys single layer wire crossing, via clock phasing, which requires only one type of cell. The results show that the proposed full adder performs equally well compared to existing multilayer designs and performs better in case of previous coplanar full adder designs in all aspects. Our design achieves 20% improvement in cell count and consumes 7% less area in comparison to the best single layer design. QCADesigner tool is used to validate the layout of the proposed designs and QCAPro power estimator tool is used to evaluate the power dissipation of all considered designs.

Reversible nanorouter using QCA for nanocommunication

In reversible nanocomputing, an emerging area of research is quantum dot cellular automata (QCA)-based design of cost-effective reversible nanocircuits. In a digital nanocommunication system, the router is the heart of data transmission. At nanoscale, for data communication the device density and energy dissipation of the circuit are key issues. A reversible circuit exhibits low energy dissipation or ideally no energy dissipation. This paper presents the design of a Fredkin gate- and a BJN gate-based design of reversible 4:1 multiplexer and 1:4 demultiplexer based on QCA with quantum costs of 15 and 30 respectively and garbage output of six and ten respectively. The proposed reversible multiplexer and demultiplexer are used to achieve a reversible nanorouter in QCA for the first time, with a quantum cost of 40 and garbage output of 16. The proposed reversible nanorouter could be used to achieve a nanocommunication system in the near future at the nanoscale low energy level. A QCA device is used to implement the proposed reversible circuits, to achieve a low-energy nanoscale circuit. The comparison of simulation consequences of proposed circuits with theoretical knowledge established the functional efficiency of the circuit.

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation- and defect-aware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement.

NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

Advances in CMOS technology have made possible the increase of integrated circuit's density, which impacts directly on the circuit's performance. However, technology scaling poses some reliability concerns that directly affect the circuit's lifetime. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits' paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of Integrated Circuits (ICs) is proposed. In more detail, the technique is based on an on-chip sensor able to monitor IC's aging and to adjust its power supply voltage in order to minimize NBTI effects and increase the circuit's lifetime. Experimental results obtained throughout simulations demonstrate the technique's efficiency, since the circuit's lifetime has been increased by 150 %. Finally, the analysis of the main overheads introduced as well as the impact related to process variation renders the evaluation of the proposed approach possible.

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit's permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.

An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits

We develop an evaluation framework to assess the potential benefits of feature-level heterogeneous integration (HGI) in nanoscale VLSI circuits. We study, for the first time, the impact of HGI on circuit delay, layout area, and power by comparing the integration of 15-nm InGaAs and Ge FinFETs via nanotransfer printing with the baseline Si-only FinFET technology. To properly account for the performance, power, and area tradeoffs, we perform comprehensive evaluations, including synthesis, placement, and routing of digital circuit benchmarks. We show the circuits designed with an HGI exhibit lower delay and power due to improved device performance at the cost of larger area induced by misalignment errors. We also demonstrate that the HGI misalignment area penalties can be drastically reduced using posttransfer fin trimming. Our findings provide substantial motivation for industry to explore HGI as a technology route for the post-Si era.

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

Molecular-Scale Electronics: From Concept to Function.

Creating functional electrical circuits using individual or ensemble molecules, often termed as "molecular-scale electronics", not only meets the increasing technical demands of the miniaturization of traditional Si-based electronic devices, but also provides an ideal window of exploring the intrinsic properties of materials at the molecular level. This Review covers the major advances with the most general applicability and emphasizes new insights into the development of efficient platform methodologies for building reliable molecular electronic devices with desired functionalities through the combination of programmed bottom-up self-assembly and sophisticated top-down device fabrication. First, we summarize a number of different approaches of forming molecular-scale junctions and discuss various experimental techniques for examining these nanoscale circuits in details. We then give a full introduction of characterization techniques and theoretical simulations for molecular electronics. Third, we highlight the major contributions and new concepts of integrating molecular functionalities into electrical circuits. Finally, we provide a critical discussion of limitations and main challenges that still exist for the development of molecular electronics. These analyses should be valuable for deeply understanding charge transport through molecular junctions, the device fabrication process, and the roadmap for future practical molecular electronics.

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill

At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication

Quantum-dot cellular automata (QCA) is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the Feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is proposed. The detection of errors in the received message during transmission is also explored. The proposed QCA Feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility of QCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless nanocommunication architecture such as nano-transmitters and nano-receivers.

Stable and metallic borophene nanoribbons from first-principles calculations

The high electronic conductance and structural stabilities enable the edge-reconstructed borophene nanoribbons to be promising electrical connections in nanoscale circuits.