Nano-crossbar Arrays Research Articles

An Accelerated Variable Stage Size Carry Skip Adder Realization Using 1S1R Resistive Memory

In-memory computing is the method of running computer computations completely in memory. Memristive device (e.g., 1 selector-1 resistor (1S1R)) is preferably utilized for in-memory computing with the appearance of hybrid CMOS nano-crossbar arrays. The parallelism of resistive arrays is considered in parallel adder designs to reduce the critical path delay. However, they minimize latency at the cost of hardware resources. In addition, the resistive random-access memory (ReRAM) is suffered by sneak–path problem because of the incapability for accessing a specific cell without impeding its neighbors. To tackle this issue, an analytical model of Pt/TaO[Formula: see text]/TiO2/TaO[Formula: see text]/Pt selector device is developed and it is integrated with ReRAM model for reducing the sneak path current. In this paper, a novel mapping scheme is proposed for in-memory variable stage size carry skip adder (VSS-CSKA) to harness the parallelism of 1S1R resistive memory. The VSS-CSKA considers variable block lengths and uses basic Boolean functions as skip logic to improve the speed without requiring huge area. Also, the selector device is modeled by considering the Pt/TaO[Formula: see text]/TiO2/TaO[Formula: see text]/Pt crested barrier for suppressing the sneak current in the resistive memory. The macro-model of the 1S1R resistive memory model is modeled in Verilog-A netlist and the simulations are executed on Spectre circuit simulator from Cadence Virtuoso. The proposed in-memory adder reduced the latency to [Formula: see text] for [Formula: see text]-bit addition and it consumes less energy because of the minimization of sneak currents in 1S1R.

Selective Overview of 3D Heterogeneity in CMOS.

As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human–world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.

Implementation of Symmetric Functions Using Memristive Nanocrossbar Arrays and their Application in Cryptography

VLSI technology makes the integration of multiple electronic components into a single electronic chip possible but Moore has already predicted that further miniaturization of VLSI chips will cause excess heat dissipation. Because of this impediment faced by this technology, the scientists have turned their focus to nano-technological alternatives to keep up the continuous device improvement and continue with the miniaturization procedure without facing any hurdle from the aspect of heat dissipation and space and time complexity. Memristor can be such a nano-alternative, which has the potential of very rapid execution, miniaturization and very low power consumption compared to transistor-based technology. The main objective of this paper is to show an application of symmetric function in cryptography. In order to do so, first, three-input and five-input symmetric functions are implemented in memristor-based nanocrossbar circuits. Then a dynamic circuit of symmetric functions is implemented where the input voltages convert the circuit to three-input or five-input symmetric function circuit as and when required. The simulation results show the satisfactory behavior of our proposed design.

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS with the drawback of higher fault rates. They offer area and power efficiency in terms of their easy-to-fabricate and dense physical structures. They consist of regularly placed crosspoints as computing elements, which behave as diode, memristor, field effect transistor, or novel four-terminal switching devices. In this study, we establish a complete design framework for crossbar circuits explaining and analyzing every step of the process. We comparatively elaborate on these technologies in the sense of their capabilities for computation regarding area including a new logic synthesis technique for memristors, fault tolerance including a novel paradigm for four-terminal devices, delay, and power consumption. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and fault rates of the given crossbar as well as their effects on performance metrics including power, delay, and area.

A Fast Logic Mapping Algorithm for Multiple-Type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays

Unlike conventional CMOS circuits, nano-crossbar arrays have considerably high defect rates. Multiple-type defects randomly occur both on crosspoint switches and wires that substantially complicates the design phase of the circuits with an elimination of systematic design choices. In order to overcome this problem, a logic mapping methodology is presented in this paper. A fast heuristic algorithm using pre-mapping logic morphing, defect oriented adaptive sorting, matching with Hadamard multiplication, and backtracking is introduced. The proposed algorithm covers both crosspoint defects including stuck-open and stuck-closed types and wire defects including bridging and broken types. Effects of stuck-closed defects, mostly disregarded in the literature, are studied in depth. In simulations, an industrial benchmark suit is used for obtaining runtime and success rate values of the proposed algorithm in comparison with those of the existing algorithms in the literature. A relative accuracy evaluation is also given in comparison with exact mapping techniques. Finally, the steps of the algorithm that are based on pre-mapping and heuristic matching techniques, are separately justified with experimental results.

Analyses of a 1-layer neuromorphic network using memristive devices with non-continuous resistance levels

The emerging nonvolatile memory technology of redox-based resistive switching (RS) devices is not only a promising candidate for future high density memories but also for computational and neuromorphic applications. In neuromorphic as well as in memory applications, RS devices are configured in nanocrossbar arrays, which are controlled by CMOS circuits. With those hybrid systems, brain-inspired artificial neural networks can be built up and trained by using a learning algorithm. First works on hardware implementation using relatively large and high current level RS devices are already published. In this work, the influence of small and low current level devices showing noncontinuous resistance levels on neuromorphic networks is studied. To this end, a well-established physical-based Verilog A model is modified to offer continuous and discrete conduction. With this model, a simple one-layer neuromorphic network is simulated to get a first insight and understanding of this problem using a backpropagation algorithm based on the steepest descent method.

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72 percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.

Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

In this work, we study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a four-terminal switch controlled by a Boolean literal. These types of arrays are commonly called as switching lattices. We propose optimal and heuristic algorithms that minimize lattice sizes to implement a given Boolean function. The algorithms are mainly constructed on a technique that finds Boolean functions of lattices having independent inputs. This technique works recursively by using transition matrices representing columns and rows of the lattice. It performs symbolic manipulation of Boolean literals as opposed to using truth tables that allows us to successfully find Boolean functions having up to 81 variables corresponding to a 9 × 9-lattice. With a Boolean function of a certain sized lattice, we check if a given function can be implemented with this lattice size by defining the problem as a satisfiability problem. This process is repeated until a desired solution is found. Additionally, we fix the previously proposed algorithm that is claimed to be optimal. The fixed version guarantees optimal sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed algorithms by considering lattice sizes and runtimes in comparison with the recently proposed three algorithms.

Composition of switching lattices for regular and for decomposed functions

Multi-terminal switching lattices are typically exploited for modeling switching nano-crossbar arrays that lead to the design and construction of emerging nanocomputers. Typically, the circuit is represented on a single lattice composed by four-terminal switches. In this paper, we propose a two-layer model in order to further minimize the area of regular functions, such as autosymmetric and D-reducible functions, and of decomposed functions. In particular, we propose a switching lattice optimization method for a special class of “regular” Boolean functions, called autosymmetric functions. Autosymmetry is a property that is frequent enough within Boolean functions to be interesting in the synthesis process. Each autosymmetric function can be synthesized through a new function (called restriction), depending on less variables and with a smaller on-set, which can be computed in polynomial time. In this paper we describe how to exploit the autosymmetry property of a Boolean function in order to obtain a smaller lattice representation in a reduced minimization time. The original Boolean function can be constructed through a composition of the restriction with some EXORs of subsets of the input variables. Similarly, the lattice implementation of the function can be constructed using some external lattices for the EXORs, whose outputs will be inputs to the lattice implementing the restriction. Finally, the output of the restriction lattice corresponds to the output of the original function. Experimental results show that the total area of the obtained lattices is often significantly reduced. Moreover, in many cases, the computational time necessary to minimize the restriction is smaller than the time necessary to perform the lattice synthesis of the entire function. Finally, we propose the application of this particular lattice composition technique, based on connected multiple lattices, to the synthesis on switching lattices of D-reducible Boolean functions, and to the more general framework of lattice synthesis based on logic function decomposition.

Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays

Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O ( log 2 N ), and the device count is 5 N . We verify the correctness of the proposed scheme by means of TaO × device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices.

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

Nano-crossbar arrays have emerged as a promising and viable technology to improve computing performance of electronic circuits beyond the limits of current CMOS. Arrays offer both structural efficiency with reconfiguration and prospective capability of integration with different technologies. However, certain problems need to be addressed, and the most important one is the prevailing occurrence of faults. Considering fault rate projections as high as 20% that is much higher than those of CMOS, it is fair to expect sophisticated fault-tolerance methods. The focus of this survey article is the assessment and evaluation of these methods and related algorithms applied in logic mapping and configuration processes. As a start, we concisely explain reconfigurable nano-crossbar arrays with their fault characteristics and models. Following that, we demonstrate configuration techniques of the arrays in the presence of permanent faults and elaborate on two main fault-tolerance methodologies, namely defect-unaware and defect-aware approaches, with a short review on advantages and disadvantages. For both methodologies, we present detailed experimental results of related algorithms regarding their strengths and weaknesses with a comprehensive yield, success rate and runtime analysis. Next, we overview fault-tolerance approaches for transient faults. As a conclusion, we overview the proposed algorithms with future directions and upcoming challenges.

Effect of adding a polymer and varying device size on the resistive switching characteristics of perovskite nanocubes heterojunction

Emerging resistive switching devices are believed to play a vital role in realizing ultra-dense nanocrossbar arrays for the next generation mass storage memory. This work reports the resistive switching effect in organic-inorganic hybrid nanocomposite of perovskite oxide zinc stannite nanocubes (ZnSnO3 NCs) and a polymer Poly(methyl methacrylate) (PMMA). The functional layer was sandwiched between indium tin oxide (ITO) and silver (Ag) electrodes on a flexible PET substrate. The obtained electrical results clearly exhibited that the addition of PMMA in ZnSnO3 NCs enhanced electrical endurance (500 biasing cycles), retention time (∼104 s), switching ratio (∼103) and repeatability of our memory device. Moreover the effect of device size on the resistive switching characteristics of this hybrid nanocomposite is also explored by varying the diameter of top electrode. The whole device fabrication except bottom layer was done through all printed technology such as electrohydrodynamic atomization (EHDA) and inkjet reciprocating head. The developed memory device displayed characteristic bipolar, nonvolatile and rewritable memory behavior at a low operating voltage. The obtained results of chemical, structural, electrical and surface morphology are added to completely understand the impact of adding a polymer on the switching characteristics of perovskite NCs.

Logic synthesis and testing techniques for switching nano-crossbar arrays

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.

Realization of Boolean Logic Functionality Using Redox‐Based Memristive Devices

Emerging resistively switching devices are thought to enable ultradense passive nanocrossbar arrays for use as random access memories (ReRAM) by the end of the decade, both for embedded and mass storage applications. Moreover, ReRAMs offer inherent logic‐in‐memory (LIM) capabilities due to the nonvolatility of the devices and therefore great potential to reduce the communication between memory and calculation unit by alleviating the so‐called von Neumann bottleneck. A single bipolar resistive switching device is capable of performing 14 of 16 two input logic functions in the logic concept presented by Linn et al. (“CRS‐logic”). In this paper, five types of selectorless devices are considered to validate this CRS‐logic concept is experimentally by means of the IMP and AND logic operations. As reference device a TaO x ‐based ReRAM cell is considered, which is compared to three more advanced device configurations consisting either of a threshold supported resistive switch (TS‐ReRAM), a complementary switching device (CS), or a complementary resistive switch (CRS). It is shown that all of these devices offer the desired LIM behavior. Moreover, the feasibility of XOR and XNOR operations using a modified logic concept is applied for both CS and CRS devices and the pros and cons are discussed.

Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model

Resistive switching devices are an emerging class of non-volatile memory elements suited for application in passive nano-crossbar arrays. These devices can be modeled as dynamical systems, i.e. memristive devices or memristors for short. The built-in non-linear switching kinetics of these devices enables the performance of ‘stateful’ logic operations and widens the applicability of memory arrays towards logic operations. In this work, two logic-in-memories approaches are studied by means of dynamical simulations. The first one is the initial ‘stateful’ logic concept introduced by Boghetti et al., and the second approach is the complementary switch-based concept later suggested by Linn et al. In both cases, the considered device is an electrochemical metallization cell for which good dynamical models are available. The study is limited to the comparison of elementary logic functions—multi-stage logic as well as parallelization features of both approaches are not considered here. A comparison of the elementary logic IMP and NAND operations in terms of reliability, switching energy and basic array compatibility is conducted, and crucial requirements for both approaches are identified.

A novel digital logic implementation approach on nanocrossbar arrays using memristor-based multiplexers

This paper presents and evaluates a novel multiplexer (MUX) composed of memristive devices and nanowire crossbar arrays. The switching behavior of memristors is employed to reveal the desired output state. By applying a sequence of appropriate voltage pulses to the developed MUX, the output is derived and can be transferred through read/write CMOS circuitry. The performance is verified with the SPICE simulator including a threshold-type memristor model. Using the proposed MUXes instead of memristor-based NAND gates, the routing effects that are a major challenge for implementing combinational logic in hybrid circuits can be reduced. Our evaluation results show that both density and delay are effectively improved in pure-MUX-based fabrics.

Dual-Direction Nanocrossbar Array ESD Protection Structures

This letter reports a new nanocrossbar array ESD protection design. The unique nanocrossbar array structures ensure uniform ESD discharging and achieve fast ESD response speed and >; 8A ESD protection capability in prototypes. The nanoswitching ESD protection effect eliminates large leakage current inherent to traditional p-n-junction-type ESD protection devices.

Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays

Recently, the sneak-path obstacle in passive crossbar arrays has been overcome by the invention of complementary resistive switches (CRSs) consisting of two bipolar antiserially connected memristive elements. Here, we demonstrate the vertical integration of CRS cells based on Cu/SiO2/Pt bipolar resistive switches. CRS cells were fabricated and electrically characterized, showing high resistance ratios (Roff/Ron >; 1500) and fast switching speed (<; 120 μs). The results are one step further toward the realization of high-density passive nanocrossbar-array-based gigabit memory devices.

Complementary Resistive Switches (CRS): High speed performance for the application in passive nanocrossbar arrays

ABSTRACTIn this report, the fabrication and electrical characterization of fully vertically integrated complementary resistive switches (CRS), which consist of two anti-serially connected Cu-SiO2 memristive elements, is presented. The resulting CRS cells are initialized by a simple procedure and show high uniformity of resistance states afterwards. Furthermore, the CRS cells show high switching speeds below 50 ns, making them excellent building blocks for next generation non-volatile memory based on passive nanocrossbar arrays.