N2O Plasma Treatment Research Articles

Growth of high quality polycrystalline InGaO thin films by spray pyrolysis for coplanar thin-film transistors on polyimide substrate

The current mobile devices are moving towards flexible electronics. Introducing crystalline oxide semiconductors on flexible substrates is important to satisfy the requirements of high-resolution displays on flexible substrates. This study investigates the low-cost, as-grown polycrystalline (Poly) InGaO thin film transistor by spray pyrolysis on polyimide (PI) substrate. Grazing Incidence X-ray Diffraction (GI-XRD) measurements demonstrate that In0.8Ga0.2O, In0.7Ga0.3O, and In0.5Ga0.5O compositions exhibit crystallization on-set temperatures of ∼330, ∼350, and ∼415°C, respectively. Poly-In0.7Ga0.3O thin film with lower oxygen-vacancy (∼15 %) and less than 5 % O-H group could be achieved at the substrate temperature of 370°C. The hysteresis-free device performance with an average saturation mobility of 43.73 cm2V−1s−1 has been obtained using the poly-In0.7Ga0.3O with optimized N2O plasma treatment on the poly-oxide thin film. The TFTs show remarkable stability under humid environments and various stress conditions such as positive bias temperature, negative bias temperature, and mechanical stresses. In addition, the 96-stage gate shift register made of poly-In0.7Ga0.3O TFTs by spray pyrolysis exhibits the rising and falling times of less than 820 ns. Therefore, the poly-In0.7Ga0.3O TFTs by spray pyrolysis could be used for high-resolution, cost-effective, flexible active-matrix light-emitting displays.

P‐97: Improved Electrical Performance and Realiability of a‐IGZO TFT by N2O Plasma Treatment Optimization

This study investigates the abnormal reliability degradations observed under positive bias temperature stress (PBTS) in a‐IGZO TFTs treated by N2O plasma treatment and proposes a solution according to the presence of N2O plasma in the subsequent postprocess. In mass manufacture of a‐IGZO TFTs, N2O plasma is usually completely removed during the subsequent post‐plasma treatment processes. However, we maintained the presence of N2O plasma and analyzed its effect on device performance and reliability. While a‐IGZO TFTs fabricated with N2O plasmaremoved during the post‐process exhibited non‐ideal negative Vth shifts under PBTS, the devices fabricated with N2O plasma present during post‐processing showed superior electrical performance and reliability, avoiding the non‐ideal Vth shift phenomenon. This study shows that maintaining N2O plasma during the post‐process is an effective method for ensuring device reliability as well as improved performance of a‐IGZO TFTs in mass production.

P‐2: Investigation of high mobility crystalline IGO TFT with top‐gate structure for LCD display application

The present paper reports the study of electrical characteristics and bias temperature stress (BT) stability of crystalline Indium‐Gallium oxide (IGO) dual‐gate thin film transistor (TFT) with top‐gate structure. TFT with normalized Ion over 100εA and PBTS/NBTIS of 0.35/‐2.85V was successfully fabricated. By adjusting oxygen partial pressure (O2%) and substrate temperature, we can control the wet etching rate (WER) of as‐deposited IGO film. After post annealing, crystalline IGO containing In2O3 phase with preferred orientation of (222) has been formed. The TFT characteristics uniformity and BT stability were found to depend on parameters of gate insulator (GI) deposition and pre‐treatment before GI. Based on experimental results, we propose high GI deposition temperature associated with low N2O plasma treatment power as the optimal condition for industrial production of crystalline IGO TFT.

Research on the β-Ga2O3 Schottky barrier diodes with oxygen-containing plasma treatment

This Letter reports two kinds of oxygen-containing plasma treated β-Ga2O3 Schottky barrier diodes (SBDs), including N2O plasma treatment and O2 plasma treatment, and the SBD without plasma is prepared for comparison. I–V characteristics, breakdown characteristics, and trap state characteristics of three devices have been studied. It is found that the turn-on voltage of SBDs with N2O plasma can reduce to 0.6 V, and the better current density of 750 A/cm2 and an on-resistance of 3.5 mΩ cm2 are obtained after the N2O plasma treatment. Moreover, the breakdown voltage of SBDs with N2O plasma is 50.2% higher than the conventional one, whose value reaches 323 V. In addition, the trap states' characteristics of the devices are studied, which show that the oxygen-containing plasma can reduce the deep level trap states density partly in the anode region, which can improve the surface quality effectively.

P‐2: Nitrogen Behaviors in PEALD‐Grown SiO2 Films Using N2O Plasma Reactant and Its Application in ALD‐IZO TFTs

We studied nitrogen (N) behaviors in plasma‐enhanced atomic layer deposition (PEALD)‐grown silicon dioxide (SiO2) using nitrous oxide (N2O) plasma reactant. The gradually improved breakdown phenomenon is attributed to N contents. However, although increase in the N contents, excess plasma power is degraded electrical characteristics. For applications of the SiO2 films using N2O plasma reactant, we fabricated indium‐zinc oxide top‐gate thin film transistors with SiO2 gate insulator (G.I). The stable both transfer characteristics and instability results are originated from decrease in oxygen vacancy in active layer by N2O plasma treatment during the G.I deposition.

Influence of N2O plasma treatment on PET-based flexible bending sensors with ZnO nanorod array cross-linked with interdigitated electrode structures

We present a highly sensitive bending sensor fabricated with hydrothermally grown zinc oxide nanorod (NR) arrays cross-linked with interdigitated electrode patterns on polyethylene terephthalate substrates. To examine the effects of microstructural change in NR arrays on the device characteristics, N2O plasma treatment (PT) was carried out for 3 and 6 min for the seed layers. Negative resistance change (ΔR) was obtained in the case of convex bending, while positive ΔR was measured under the concave bending from every device prepared under different PT conditions, which is due to the change in the number of cross-linkings between the NRs. The device with no PT condition showed the highest gauge factor of 196 at a bending strain of 1.75% in the convex direction.

N2O plasma treatment effect on reliability of p-GaN gate AlGaN/GaN HEMTs

This work investigates the effect of N2O plasma treatment on the reliability of p-GaN gate AlGaN/GaN high-electron-mobility transistors (HEMTs), specifically in the AlGaN drift region. The formation of a GaON/AlON compound layer on the AlGaN surface after N2O plasma treatment was confirmed by energy-dispersive x-ray spectroscopy mapping and x-ray photoelectron spectroscopy analysis. When a device is under highly stressed conditions, the compound layer reduces the number of negatively charged interface traps and protects the AlGaN surface by hindering the Ga-out diffusion. The high temperature reverse bias reliability test demonstrated that the N2O plasma treatment enhanced the reliability of p-GaN gate HEMTs by suppressing the degradation of the on-resistance from 18.7% to 9.0%, after being subjected to a high drain bias (VDS = 700 V) at 200 °C for 1000 s.

The effect of passivation-layer process to amorphous InGaZnO thin-film transistors using back-channel etch method

In this work, based on the channel damage caused by source/drain etching and passivation-layer deposition, the effects of the passivation-layer process on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) devices were studied by combining experimental investigation with simulation verification. In terms of experimental exploration, it was found that the back-channel N2O plasma treatment had a significant impact on the performance of the device, which was difficult to control. Hence, to achieve a low cost, the entire back-channel process was directly carried out as two steps of SiO x passivation-layer deposition and final thermal annealing. In the aspect of simulation verification, the influence of the passivation-layer deposition radio-frequency (RF) power and the annealing effect on the internal mechanism of the device was studied based on a high-concentration doped defect density of states (DOS) model (doping level was N D = 1020 cm−3). The experimental results demonstrated that the high-performance of an a-IGZO TFT device can be achieved by adjusting the RF power of SiO x passivation-layer deposition. It was more important that annealing after passivation-layer deposition was a critical step in the manufacture of high-performance TFTs. The device exhibited the ideal performance after annealing under 1000 W RF power, with a threshold voltage of 5.65 V, a saturation mobility of 12.87 cm2 V−1s−1, a subthreshold swing of 0.88 V dec−1, and a current on-off ratio of 2.62 × 10°8. In addition, using the DOS model, it was found that the SiO x passivation-layer process had a significant impact on the DOS distribution and the carrier distribution in the channel, which in turn caused the threshold voltage to drift. At last, the high uniformity and stability of an a-IGZO TFTs array on glass were characterized.

High linearity AlGaN/GaN HEMT with double-V th coupling for millimeter-wave applications

We demonstrated an AlGaN/GaN high electron mobility transistor (HEMT) namely double-V th coupling HEMT (DVC-HEMT) fabricated by connecting different threshold voltage (V th) values including the slant recess element and planar element in parallel along the gate width with N2O plasma treatment on the gate region. The comparative studies of DVC-HEMT and Fin-like HEMT fabricated on the same wafer show significantly improved linearity of transconductance (G m) and radio frequency (RF) output signal characteristics in DVC-HEMT. The fabricated device shows the transconductance plateau larger than 7 V, which yields a flattened f T/f max-gate bias dependence. At the operating frequency of 30 GHz, the peak power-added efficiency (PAE) of 41% accompanied by the power density (P out) of 5.3 W/mm. Furthermore, the proposed architecture also features an exceptional linearity performance with 1-dB compression point (P 1 dB) of 28 dBm, whereas that of the Fin-like HEMT is 25.2 dBm. The device demonstrated in this article has great potential to be a new paradigm for millimeter-wave application where high linearity is essential.

Visible to near-infrared photodetector based on SnSe2/WSe2 heterojunction with potential application in artificial visual neuron

Two-dimensional (2d) transition-metal dichalcogenides (TMDCs) are promising candidate materials for developing next generation nano optoelectronic devices, due to their strong interaction with light. In addition, the free of surface dangling bonds makes it possible to stacking any different types of 2D TMDCs together to form heterojunctions with desirable band structures for various applications. However, most of the 2D TMDCs are bipolar or strong unipolar n-type doped, while very few of them show weak p-type doping, which severely affects the performance of the formed heterojunctions. In this work, we fabricated a SnSe2/WSe2 heterojunction of type II band alignment with a small bandgap of ∼0.1 eV, which is ideally for developing optoelectronic devices responsible to a broad light spectrum. N2O plasma treatment is applied to enhance the p-type doping of both WSe2 and SnSe2, which results in the increased on–off ratio of n-type SnSe2 by 50 times and the hole mobility of WSe2 by 527 times. The WSe2/SnSe2 heterostructure also achieves a decent performance as a p–n junction, which exhibits photo responsivity of 450 mA W−1 and 133 mA W−1 for 700 nm visible light and 1600 nm infrared light, respectively, without any gate or source-drain bias, showing great photovoltaic effect. Moreover, the heterojunction shows great promise as an artificial visual neuron, which can differentiate the dark, visible and infrared light illumination conditions by applying a series of electrical pulses through the back-gate electrode.

Effects of Seed-Layer N2O Plasma Treatment on ZnO Nanorod Based Ultraviolet Photodetectors: Experimental Investigation with Two Different Device Structures.

The crystalline quality of ZnO NR (nanorod) as a sensing material for visible blind ultraviolet PDs (photodetectors) critically depends on the SL (seed layer) material of properties, which is a key to high-quality nanocrystallite growth, more so than the synthesis method. In this study, we fabricated two different device structures of a gateless AlGaN/GaN HEMT (high electron mobility transistor) and a photoconductive PD structure with an IDE (interdigitated electrode) pattern implemented on a PET (polyethylene terephthalate) flexible substrate, and investigated the impact on device performance through the SL N2O plasma treatment. In case of HEMT-based PD, the highest current on-off ratio (~7) and spectral responsivity R (~1.5 × 105 A/W) were obtained from the treatment for 6 min, whereas the IDE pattern-based PD showed the best performance (on-off ratio = ~44, R = ~69 A/W) from the treatment for 3 min and above, during which a significant etch damage on PET substrates was produced. This improvement in device performance was due to the enhancement in NR crystalline quality as revealed by our X-ray diffraction, photoluminescence, and microanalysis.

Enhancement in the photonic response of ZnO nanorod-gated AlGaN/GaN HEMTs with N2O plasma treatment.

We demonstrate an improvement in the photoresponse characteristics of ultraviolet (UV) photodetectors (PDs) using the N2O plasma-treated ZnO nanorod (NR) gated AlGaN/GaN high electron mobility transistor (HEMT) structure. The PDs fabricated with ZnO NRs plasma-treated for 6 min show superior performance in terms of responsivity (∼1.54×10 5 A/W), specific detectivity (∼ 4.7×1013 cm·Hz-1/2/W), and on/off current ratio (∼40). These improved performance parameters are the best among those from HEMT-based PDs reported to date. Photoluminescence analysis shows a significant enhancement in near band edge emission due to the effective suppression of native defects near the surface of ZnO NRs after plasma treatment. As our X-ray photoelectron spectroscopy reveals a very high O/Zn ratio of ∼0.96 from the NR samples plasma-treated for 6 min, the N2O plasma radicals also show a clear impact on ZnO stoichiometry. From our X-ray diffraction analysis, the plasma-treated ZnO NRs show much greater improvement in (002) peak intensity and degree of (002) orientation (∼0.996) than those of as-grown NRs. This significant enhancement in (002) degree of orientation and stoichiometry in ZnO nano-crystals contribute to the enhancement in photoresponse characteristics of the PDs.

Defect gradient control in amorphous InGaZnO for high-performance thin-film transistors

The accuracy control of oxygen-correlated defect densities in the lattice of metal oxide semiconductors is one of the remaining issues restricting the performance of metal oxide-based devices and their commercialization process. This study has successfully realized the gradient control of defects in amorphous InGaZnO through various strategies. X-ray photoelectron spectroscopy results reveal that the 350 °C thermal annealing accompanied with 300 °C pre-treatment is more conducive to improve the quality of a-IGZO and suppress the density of oxygen vacancy defects. Correspondingly, the initial electrical properties of a-IGZO thin-film transistor treated by gradient annealing procedures is superior to those of the devices with one-step 350 °C routine annealing or combined with an intermediate N2O plasma treatment. It is demonstrated that the gradient annealing procedures effectively improve the quality of a-IGZO bulk and its adjacent interfaces. More importantly, the notorious instability induced by the negative bias and illumination stress is significantly suppressed.

High performance anatase-TiO2 thin film transistors with a two-step oxidized TiO2 channel and plasma enhanced atomic layer-deposited ZrO2 gate dielectric

We reported high performance anatase-TiO2 thin film transistors with a two-step oxidized TiO2 channel (O2 annealing and N2O plasma treatment) and O2 plasma enhanced atomic layer-deposited ZrO2 gate dielectric. The transistors using 60 nm TiO2 as the active channel exhibited a steep subthreshold swing of 112 mV dec−1 and a high on/off current ratio of 1.4 × 108. The superior performances, achieved by the two-step oxidizing process and the utilization of ZrO2 as the high-k gate dielectric, show their great potential to be applied in future electronic and optical systems, such as active-matrix displays and ultraviolet sensors.

Implementation of Self-Aligned Top-Gate Amorphous Zinc Tin Oxide Thin-Film Transistors

Self-aligned top-gate (SATG) amorphous zinc tin oxide thin-film transistors (a-ZTO TFTs) are fabricated for the first time. Ar plasma treatment forms the self-aligned source/drain (S/D) region and reduces the sheet resistance of the a-ZTO S/D region from a very high value over the measurable limit to around 2.5 $\text{k}\Omega $ /□. The annealing temperature of the a-ZTO film has a strong impact on the electrical performances of the fabricated TFTs. The N2O plasma treatment prior to gate insulator deposition remarkably enhances the TFT performances. The fabricated a-ZTO TFTs present a field-effect mobility of 12.1 ± 0.27 cm $^{\textbf {2}}/\textsf {V}\cdot \textsf {s}$ , a subthreshold swing of 0.3 ± 0.03 V/decade, and good electrical stress stability under both positive and negative biases. A low-cost SATG a-ZTO TFT technology is thus well demonstrated.

The role of the sequence of plasma treatment and high temperature annealing on solution-processed a-IMZO thin film transistor

In this paper, we reported the effects of the order of plasma treatment and high temperature annealing on solution-processed amorphous indium magnesium zinc oxide (a-IMZO, In:Ga:Zn = 3:1:1) thin film transistors (TFTs). Specifically, we utilized two different processes to fabricate TFTs. In one process, the active layers were plasma-treated (PT, 10 W, 10min) before high temperature thermal annealing (TA, 400 °C), and in another process, the active layers were plasma-treated after high temperature annealing. The former achieves lower off-current (5.83 × 10−12 A) and larger on/off current ratio (2.2 × 107), because the oxygen-related ions in the N2O plasma treatment can passivate the surface of the active layer and reduce the residual organic groups. However, introducing of O2+ and O2− ions leads to an increase in interface defects. The latter sample reaches a mobility 1.97 cm2/V·s, as the generated nanopores during high temperature annealing provide path for more atomic oxygen to infiltrate the film during PT and the oxygen vacancies are reduced. However, the on-current drops sharply with plasma treatment power for the increase of oxidation depth. In addition, all the PT samples show small hysteresis and improved stabilities. Our study suggests that moderate plasma treatment can be adopted to improve the a-IMZO TFT device performances.

Record combination fmax · Vbr of 25 THz·V in AlGaN/GaN HEMT with plasma treatment

A combination of high maximum oscillation frequency (fmax) and breakdown voltage (Vbr) was achieved in AlGaN/GaN high electron mobility transistors (HEMTs) with N2O plasma treatment on the access region. The breakdown voltage is improved from 37 V to 80 V due to the formation of oxide layer in the gate region. A suppressed current collapse is obtained due to plasma treatment on the gate-source and the gate-drain regions. The effect of the present passivation method is almost the same with that of the conventional SiN passivation method, meanwhile it can avoid introducing additional parasitic capacitance due to thinner thickness. The small signal measurement shows that HEMT can yield fT and fmax of 98 and 322 GHz, respectively, higher than that of 70 and 224 GHz for the non-treated HEMT. By using the plasma treatment technique, the HEMT can simultaneously exhibit high fmax and Vbr with a record fmax⋅Vbr of 25 THz⋅V.

Improved performance of fully-recessed normally-off LPCVD SiN/GaN MISFET using N2O plasma pretreatment

An effective and simple approach for gate-recessed normally-off GaN-based MISFETs is proposed to suppress the high temperature induced degradation during low pressure chemical vapour deposition (LPCVD) in gate-recessed normally off GaN-based MISFET. After a N2O plasma treatment on GaN channel prior to LPCVD SiN, the LPCVD SiN/GaN MISFET exhibits a maximum drain current of 607 mA/mm, 3 times higher than that without N2O plasma pretreatment, a threshold voltage of +1.2 V at ID = 0.1 mA/mm, off-state hard-breakdown voltage of 1348 V with LGD = 20 μm, and gate leakage current below 15 nA/mm in the whole gate swing to +20 V. The interface states characterization in MISFETs show that about 3 times lower interface trap density was achieved in MISFET with N2O plasma pretreatment compared to that in SiNx/GaN transistor without such surface treatment.

Interface tailoring through the supply of optimized oxygen and hydrogen to semiconductors for highly stable top-gate-structured high-mobility oxide thin-film transistors.

Self-aligned structured oxide thin-film transistors (TFTs) are appropriate candidates for use in the backplanes of high-end displays. Although SiNx is an appropriate candidate for use in the gate insulators (GIs) of high-performance driving TFTs, direct deposition of SiNx on top of high-mobility oxide semiconductors is impossible due to significant hydrogen (H) incorporation. In this study, we used AlOx deposited by thermal atomic layer deposition (T-ALD) as the first GI, as it has good H barrier characteristics. During the T-ALD, however, a small amount of H from H2O can also be incorporated into the adjacent active layer. In here, we performed O2 or N2O plasma treatment just prior to the T-ALD process to control the carrier density, and utilized H to passivate the defects rather than generate free carriers. While the TFT fabricated without plasma treatment exhibited conductive characteristics, both O2 and N2O plasma-treated TFTs exhibited good transfer characteristics, with a Vth of 2 V and high mobility (∼30 cm2 V−1 s−1). Although the TFT with a plasma-enhanced atomic layer deposited (PE-ALD) GI exhibited reasonable on/off characteristics, even without any plasma treatment, it exhibited poor stability. In contrast, the O2 plasma-treated TFT with T-ALD GI exhibited outstanding stability, i.e., a Vth shift of 0.23 V under positive-bias temperature stress for 10 ks and a current decay of 1.2% under current stress for 3 ks. Therefore, the T-ALD process for GI deposition can be adopted to yield high-mobility, high-stability top-gate-structured oxide TFTs under O2 or N2O plasma treatment.

(Invited) High Performance UTB GeOI n and pMOSFETs Featuring HEtero-Layer-Lift-Off (HELLO) Technology

Advanced HEtero-Layer-Lift-Off (HELLO) technology utilizing Ge/SiGe/Ge hetero-epitaxy technique was implemented to realize high quality ultrathin body (UTB) Ge-on-insulator (GeOI) structures. Top interfacial quality of GeOI has been taken care by plasma enhanced ALD-Al2O3 passivation. On the other hand, bottom interfacial quality of GeOI was improved by N2O plasma treatment or Si passivation for UTB GeOI n and pMOSFETs, respectively. Besides, GeOI body thickness (T body) was precisely controlled through SiGe etch stop layer and digital etching process. For lowering parasitic resistance of S/D regions of bulk Ge n and pMOSFETs, ion implantation after germanidation (IAG) has been demonstrated as an effective way. Moreover, high performance UTB GeOI n and pMOSFETs with T body less than 5 nm have been successfully fabricated for the first time. Thickness dependence of carrier mobility of GeOI has also been investigated systematically through split-CV method, revealing a great potential of UTB GeOI structures in future Ge CMOS application.