Implementation of Self-Aligned Top-Gate Amorphous Zinc Tin Oxide Thin-Film Transistors

Abstract

Self-aligned top-gate (SATG) amorphous zinc tin oxide thin-film transistors (a-ZTO TFTs) are fabricated for the first time. Ar plasma treatment forms the self-aligned source/drain (S/D) region and reduces the sheet resistance of the a-ZTO S/D region from a very high value over the measurable limit to around 2.5 $\text{k}\Omega $ /□. The annealing temperature of the a-ZTO film has a strong impact on the electrical performances of the fabricated TFTs. The N2O plasma treatment prior to gate insulator deposition remarkably enhances the TFT performances. The fabricated a-ZTO TFTs present a field-effect mobility of 12.1 ± 0.27 cm $^{\textbf {2}}/\textsf {V}\cdot \textsf {s}$ , a subthreshold swing of 0.3 ± 0.03 V/decade, and good electrical stress stability under both positive and negative biases. A low-cost SATG a-ZTO TFT technology is thus well demonstrated.