Abstract
The key technology issues for fabrication of high performance self-aligned top gate amorphous metal oxide thinfilm transistors are addressed. These issues include the sputtering deposition of active layer of metal oxide, the PECVD growth of gate oxide, the plasma enabled interface treatment between the active layer and gate insulator, the doping method for low resistance source-drain regions, and the annealing process for performance enhancement. With these issues well addressed, high performance self-aligned top-gate TFTs with various amorphous oxide channel materials, like aIGZO, a-IZO and a-ZTO have been achieved.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.