N-type MOSFETs Research Articles

Indium doping-assisted monolayer Ga2O3 exfoliation for performance-enhanced MOSFETs.

Monolayer (ML) Ga2O3 with outstanding properties is promising for advanced nanodevice applications; however, its high exfoliation energy makes obtaining it challenging. In this study, we propose a more efficient solution to obtain ML Ga2O3 by exfoliation from indium-doped bulk β-Ga2O3. The exfoliation efficiency with the assistance of In-doping and the doping influence on the stability and structural and electronic properties of ML Ga2O3 are systematically studied using first-principles calculations. The exfoliation energy of ML Ga2O3 is found to be reduced by 28% and is of the same order of magnitude as that of typical van der Waals (vdWs) 2D materials. Besides, excellent stability is preserved for ML Ga2O3 at extremely high In doping concentration by phonon spectrum and ab initio molecular dynamics inspections. The bandgap of ML Ga2O3 decreases from 4.88 to 4.25 eV with increased In concentration, and the modification of the VBM converts ML Ga2O3 to a direct bandgap semiconductor. With the suppression of ZA mode phonon scattering, the pristine and In-doped ML Ga2O3 exhibit high electron mobility, whereas the strong electron-phonon coupling (EPC) effect significantly decreases the hole mobility. Finally, the transfer characteristics of 5 nm MOSFETs based on the pristine and In-doped ML Ga2O3 with varied In concentrations are simulated based on the non-equilibrium Green's function (NEGF) formalism. The Ion for HP has a maximum of 3060 μA μm-1 at In doping concentration of 5% and is triple that of the pristine ML Ga2O3 for LP at In doping concentration of 20%. The FOMs of n-type MOSFETs based on the In-doped ML Ga2O3 and typical 2D materials are compared and shows huge potential for sub-5 nm applications. Our study applies a new strategy for obtaining ML Ga2O3 and can also improve the device performance at the same time.

Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs With Local Oxidation of SiC Isolation

In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{th}$ </tex-math></inline-formula> ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.

Electrically Self-Aligned, Reconfigurable Test Structure Using WSe2/SnSe2 Heterojunction for TFET and MOSFET

Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SnSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance.

High-Performance and Low-Power Transistors Based on Anisotropic Monolayer β - TeO2

Two-dimensional (2D) semiconductors offer a promising prospect for high-performance and energy-efficient devices especially in the sub-10-nm regime. Inspired by the successful fabrication of 2D \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ and the high on:off ratio and high air stability of fabricated FETs [Zavabeti et al., Nat. Electron. 4, 277 (2021)], we provide a comprehensive investigation of the electronic structure of monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ and the device performance of sub-10-nm MOSFETs based on this material. The anisotropic electronic structure of monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ plays a critical role in the anisotropy of transport properties for MOSFETs. We show that the 5.2-nm gate-length n-type MOSFET holds an ultrahigh on-state current exceeding 3700 \textmu{}A/\textmu{}m according to International Roadmap for Devices and Systems (IRDS) 2020 goals for high-performance devices, which is benefited by the highly anisotropic electron effective mass. Moreover, monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ MOSFETs can fulfill the IRDS 2020 goals for both high-performance and low-power devices in terms of on-state current, subthreshold swing, delay time, and power-delay product. This study unveils monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ as a promising candidate for ultrascaled devices in future nanoelectronics.

MOSFET-Based Memristor for High-Frequency Signal Processing

This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6~\mu \text{W}$ </tex-math></inline-formula> . In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates.

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

In this study, the performance of complementary metal–oxide–semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vth were characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

In this paper, in order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer (SIT) and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanscale fins at the same time, which increase the volumes of electrical conductance pathway between NS channels and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those of w./o. LPs. Therefore, ∼3 times and ∼2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.

Analytic modeling of a hybrid power module based on diamond and SiC devices

Unlike SiC unipolar devices, the on-state resistance of diamond unipolar devices based on bulk conduction has a negative temperature coefficient (NTC) which reduces the conduction losses at high junction temperatures. Thus, in order to associate these opposed temperature coefficients, the current article focuses on the modeling of a hybrid power device composed of a n-type 4H-SiC MOSFET and a p-type diamond bulk FET device. The optimal performances and sizing of SiC and diamond devices are introduced and calculated, as an initial benchmark under the same specifications. Based on an analytical modeling of both switching and conduction losses, junction temperatures and associated heatsink parameters, the hybrid device performances are evaluated for a synchronous buck converter operating at 1200 V–1 A and at an ambient temperature of 300 K. The results described in the manuscript highlight an equilibrium of the hybrid device total losses over a large range of temperatures as well as a reduction by two of the SiC active area. The proposed analysis could be further extended to different voltage/current classes to meet the requirements of alternative applications.

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory (4T SRAM) cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32 nm technology node that the read static noise margin (SNM) of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold SNM can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

Atomic layer annealing for modulation of the work function of TiN metal gate for n-type MOS devices

Tailoring the work function of metal gates at a low temperature is critical to the electronic performance of advanced nanoscale MOSFET devices. In this paper, the work function of TiN thin films is effectively altered by the atomic layer annealing (ALA) technique, i.e. the layer-by-layer, in-situ argon plasma treatment incorporated into each atomic layer deposition cycle. The density, stoichiometry, and crystallinity of TiN thin films can be significantly improved by the ALA treatment at a low temperature of only 300℃, which leads to a wide tunability of the work function from 4.52 to 4.03 eV of the TiN metal gate. The sufficiently low work function of 4.03 eV is highly favorable to the low power consumption in n-type MOSFETs. The result indicates that the ALA technique is an advantageous approach to modulating the physical and material properties of metal gates in nanoscale MOS devices by precise energy transfer with atomic-scale accuracy.

Design and Characteristics of CMOS Inverter based on Multisim and Cadence

Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

A high rectification efficiency Si0.14Ge0.72Sn0.14-Ge0.82Sn0.18-Ge quantum structure n-MOSFET for 2.45 GHz weak energy microwave wireless energy transmission

The design strategy and efficiency optimization of a Ge-based n-type metal–oxide–semiconductor field-effect transistor (n-MOSFET) with a Si0.14Ge0.72Sn0.14–Ge0.82Sn0.18–Ge quantum structure used for 2.45 GHz weak energy microwave wireless energy transmission is reported. The quantum structure combined with δ-doping technology is used to reduce the scattering of the device and improve its electron mobility; at the same time, the generation of surface channels is suppressed by the Si0.14Ge0.72Sn0.14 cap layer. By adjusting the threshold voltage of the device to 91 mV, setting the device aspect ratio to 1 μm/0.4 μm and adopting a novel diode connection method, the rectification efficiency of the device is improved. With simulation by Silvaco TCAD software, good performance is displayed in the transfer and output characteristics. For a simple half-wave rectifier circuit with a load of 1 pf and 20 kΩ, the rectification efficiency of the device can reach 7.14% at an input power of –10 dBm, which is 4.2 times that of a Si MOSFET (with a threshold voltage of 80 mV) under the same conditions; this device shows a better rectification effect than a Si MOSFET in the range of –30 dBm to 6.9 dBm.

Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

With the quasi-3-D scaling equation, quasi-3-D minimum channel potential, and drift-diffusion model, a unified subthreshold current model for junctionless multiple-gate (JLMG) MOSFETs including quadruple-gate (QG), triple-gate (TG), and omega-gate ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \text{G}$ </tex-math></inline-formula> ) devices is developed. With this subthreshold current model, the noise margin (NM) behavior of the subthreshold logic gate composed of JLMG MOSFETs is assessed. With the same cross-sectional area of the devices, the QG MOSFET provides the largest NM among the three devices due to its smallest scaling length. On the contrary, the TG MOSFET with the largest scaling length exhibits the smallest NM. The short-channel-degraded NM behavior can be similarly seen in these devices. In terms of design triangle (DT) of subthreshold logic gate, the QG MOSFET can provide the largest DT as opposed to the smallest one supplied by the TG device. The transistor strength balance (TSB) between p-type and n-type JLMG MOSFETs can be adjusted by tuning the gate work function to implement the optimum NM design. Finally, the impact of random doping fluctuation (RDF) on NM degradation is also discussed in this work.

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation.

In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications

The internet of things (IoTs)-based systems require battery-enabled energy-efficient memory circuits to operate at low voltage domain, especially below the transistor’s threshold. This study presents a single-ended 7T SRAM cell for IoTs applications. Cell core of the proposed 7T SRAM cell is composed of a novel Schmitt-trigger circuit in which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. The proposed 7T SRAM cell employs only one bitline to perform both read and write operations to reduce active power consumption. Read operation of the proposed 7T SRAM cell is conducted using only a single n-type MOSFET transistor driven by QB node. This transistor isolates bitline from storage nodes during read operation, improving read stability (RSNM) and read delay (TRA). A p-type MOSFET controlled by write wordline is placed inside the cell core to cut its feedback path off during write operation. This mechanism eliminate writing ‘1′ issue in single-ended SRAM cell and facilitate write ‘1′ operation, resulting in write-ability (WSNM) enhancement. To prove superiority of the proposed 7T SRAM cell in the various design metrics, it is compared with six state-of-the-art SRAM cells at subthreshold supply of VDD = 0.3 V. The proposed 7T SRAM cell is the second/first/third best cell in terms of RSNM/WSNM/write access time (TWA). Furthermore, an improvement of at least 2.55X in TRA and 12.58X (2.02X) in read (write) energy consumption is achieved by the proposed 7T SRAM cell. Although, the proposed 7T SRAM cell offers some disadvantages, nevertheless it offers the best proposed figure of merit.

High Transconductance Gain Current Differencing Transconductance Amplifiers Using a New Approach of gm Boosting

Two new structures of current differencing transconductance amplifier (CDTA) for high transconductance gains are proposed. Usually, the transconductance gain of conventional CDTA is controlled by varying the bias current which limits the transconductance gain up to a certain extent and increases the power dissipation. These problems have been eliminated by introducing a technique in which common source amplifiers are connected between gate and source terminals of the differential pair metal oxide semiconductor field effect transistors (MOSFETs) of conventional CDTA. The common source amplifiers are used to increase the gate-to-source voltages of differential pair MOSFETs which increase the transconductance gain of the proposed CDTA-I. To further increase the transconductance gain of the proposed CDTA-I, another structure namely, CDTA-II is also proposed which uses an ‘N’ number of n-type MOSFETs connected in parallel instead of a single n-type MOSFET in each side of the differential pair. The gate-to-source voltages of all ‘N’ parallel MOSFETs remain the same as in the proposed CDTA-I and the total output current of operational transconductance amplifier is increased and therefore, transconductance gain is further increased. The proposed CDTA-I and CDTA-II have been designed using Mentor Graphics Eldo tool. The simulation results have been obtained using 0.18 µm complementary metal oxide semiconductor technology parameters. The simulation results demonstrate that the transconductance gains of proposed structures have been increased significantly while power dissipations are the same as that of the conventional CDTA. The high-frequency Kerwin–Huelsman–Newcomb filters using both the proposed structures have also been presented to show the effectiveness of the proposed CDTAs.

New Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET

We report a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations. The study shows the remarkable role of the SiO2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si1-xGex. We found very specific annealing conditions to relax SGOI while keeping a homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO2 at this temperature, which would allow layer-by-layer matter redistribution. Remarkably, the Si layer epitaxially grown on relaxed SGOI remains fully strained with -0.85% tensile strain. The absence of strain sharing (between Si1-xGex and Si) is explained by the rigidity of the Si1-xGex/BOX interface at low temperature. Elastic simulations of the real system show that, because of the very specific elastic characteristics of SiO2, there are unique experimental conditions that both relax Si1-xGex and keep Si strained. Various epitaxial processes could be revisited in light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switch applications and for many other applications.

Ideal Rectifier Bridge Converting the Harvested Energy of Vibrations Into Electric Energy to Power an MR Damper

Abstract The newly developed ideal rectifier bridge equipped with four N-type MOSFETs and two rail-to-rail operational amplifiers is a part of a typical energy harvesting conditioning circuit responsible for the rectification stage in the system of converting the energy harvested from vibrations into electrical energy to power the MR damper. The only energy loss in the bridge is caused by the voltage loss in transistors’ channels. The first sections of the work summarises the structural design of the bridge, the simulation procedure under the RL load and by sine voltage inputs with predetermined frequency and amplitude range, and benchmarks the results against those obtained for the conventional bridge based on Schottky diodes. In the second section, the PCB prototype of the bridge is analysed, and measurement data are compiled. The third section reports on the laboratory testing of the developed bridge converting the harvested energy in an MR damper-based vibration reduction system.

Performance Boosts in n-Type Lateral Double-Diffused MOSFET With Process-Induced Strain Using Contact Etch Stop Layer Stressor

In this brief, the contact etch stop layer (CESL) stressor is introduced to improve the performance of n-type lateral double-diffused MOSFET (nLDMOSFET) with various operating voltages. Three groups of nLDMOSFETs were studied to demonstrate the effects of the CESL stressor. The electrical properties were carefully characterized, and the tip-enhanced Raman spectroscopy measurements were carried out to examine the process-induced strain directly. It is found that nLDMOSFETs with the strained SiN CESL have larger output current, transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), and higher breakdown voltage (BV). The strained SiN CESL introduces tensile strain in the device and results in the performance boosts, which are verified by negative Raman peak shift mappings and TCAD simulations. The strained SiN CESL could effectively decrease the specific ON-resistance (Ron) and improve the BV of the nLDMOSFET, due to the mobility enhancement.

Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances.

In this paper, we adopt the vertical core-shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the p-type MOSFET (pMOSFET). Through this variation, the asymmetry of the electrical characteristics between n-type MOSFET (nMOSFET) and pMOSFET nanowire is considerably compensated. The inverter using the proposed core-shell structure shows the improved CMOS logic inverter characteristics. For example, the core-shell CMOS logic inverter shows performances such as NML = 0.315 V, NMH = 0.312 V, τPHL of 8.7 ps, and τPHL of 21 ps at an operating voltage of VDD = 0.7 V.