N-type InP Research Articles

Continuous Metal-Insulator Transition and Scale Laws in Metallic n-Type InP

We have studied the transport properties in metallic n-type InP semiconductor. We show that the dependence on temperature of metallic electrical conductivity obey to the law 𝜎 = 𝜎(𝑇 = 0) + 𝑚𝑇1/2. We highlight the absence of a minimum electrical conductivity 𝜎𝑚𝑖𝑛 proposed by Mott at the metal-insulator transition. We show that the conductivity at temperature T = 0 K, 𝜎(𝑇 = 0) , follows a scaling law as a function of the effective parallel and perpendicular Bohr radii 𝑎∥ and 𝑎⊥.

Packaging design and thermal analysis for 1 mm2 high power VCSEL

PurposeVertical-cavity surface-emitting laser (VCSEL) is a high-performance semiconductor device made of unique epitaxial layers grown on n-type GaAs or InP substrates. The VCSEL’s thermal resistance, Rth, is an essential metric that reflects its thermal properties and dependability. The purpose of this paper is to develop packaging for 1 mm2 VCSEL chips made of a variety of materials, such as ceramic, lead frame and printed circuit board (PCB)-based packaging, as well as provide an idea or design that can withstand and perform well in terms of Rth and heat dissipation during operation. SolidWorks 2017 and AutoCAD Mechanical 2017 software were used to publish all thoughts and ideas, including the size dimensions (x, y and z) and material choices for each package.Design/methodology/approachFollowing the modelling and material selection, the next step is to use the Ansys Mechanical Structural FEA Analysis software to simulate all packaging for Rth and determine which packaging produced the best result, therefore, determining the heat dissipation for each packing. All parameters were used based on the standard cleanroom requirement for the industrial manufacturing backend process, where the cleanroom classification is 10,000 particles (ISO 7). The results demonstrated that the ceramic and lead frame provided good Rth values of 7.3 and 7.0 K/W, respectively, when compared to the PCB, which provided more than 80 K/W; thus, the heat dissipation for PCB packaging also increased.FindingsAs a result of the research, it was determined that ceramic and lead frame packaging are appropriate and capable of delivering good Rth and heat dissipation values when compared to PCB. In comparison to PCB, which requires numerous modifications, such as adding via holes and a thermal bar in an attempt to lower the Rth value, neither packaging requires improvement. Ceramic was chosen for development based on Rth's highest performance, with the actual device consisting of a lead frame and PCB. The Zth measurement test was carried out on a ceramic package, and the Rth result was comparable to the simulation result of 7.6 K/W, indicating that simulation was already proved for research and development.Originality/valueThe purpose of this study is to determine which proposed packaging design would give the highest Rth performance of a 1 mm2 chip as well as the best heat dissipation. In comparison to other studies, VCSEL packaging used the header and window cap as package components with a wavelength of 850 nm, and other VCSEL packaging developments used the sub mount on ceramic package with an output power ranging from 500 mW to 2 W, whereas this study used a huge wavelength and an output power of 4 W.

Nanoscale wafer patterning using SPM induced local anodic oxidation in InP substrates

Atomic force microscopy (AFM) assisted local anodic oxidation (LAO) offers advantages over other semiconductor fabrication techniques as it is a low contamination method. We demonstrate the fabrication of deep and highly reproducible nanohole arrays on InP using LAO. Nanohole and nano-oxide mound radius and depth are controlled independently by altering AFM tip bias and humidity, with a maximum nanohole depth of 15.6 ± 1.2 nm being achieved. Additionally, the effect of tip write speed on oxide line formation is compared for n-type, p-type and semi-insulating substrates, which shows that n-type InP oxidizes at a slower rate that semi-insulated or p-type InP. Finally, we calculate the activation energy for LAO of semi-insulating InP to be 0.4 eV, suggesting the oxidation mechanism is similar to that which occurs during plasma oxidation.

Near-infrared detection in Si/InP core-shell radial heterojunction nanowire arrays

We have explored the photodetection properties of a core-shell nanowire (NW) heterojunction based device consisting of p-Si/n-InP with an aim to provide an alternative to Si based photodetector by integrating a III-V material, viz. InP with silicon. The core is p-Si NWs, prepared by metal assisted chemical etching of p-type Si (100) substrate at room temperature using Ag nanoparticles, whereas n-type InP shells were deposited by metal organic chemical vapor deposition. The current-voltage characteristics of the device resemble that of a p-n junction with good rectification ratio in the dark, and provides photoresponse under visible and near-infrared (NIR) spectral region at low reverse bias condition. In the NIR regime, it shows an on/off ratio of 23 with a rise and fall time of 387 ms and 424 ms, respectively, at a reverse bias voltage of 2 V. The device exhibits a peak responsivity and detectivity of 2.749 A/W and 5.52 × 1011 Jones, respectively, at 920 nm under the same reverse bias voltage. Thus p-SiNW/n-InP core-shell based device could have the potential to be developed as an optoelectronic device beyond the traditional p-n junction exploiting its radial heterojunction based structure.

Coupled time resolved and high frequency modulated photoluminescence probing surface passivation of highly doped n-type InP samples

Electronic passivation of III–V surfaces is essential for applications in optoelectronic devices. A key aspect is the measurement of the surface recombination properties, which can be done by various techniques including transient photoluminescence (TRPL) or luminescence quantum yield. These measurement techniques are always indirect since they suppose postulating a mathematical model for the data interpretation. Most common models use the notion of surface recombination velocity to quantify the surface recombination. In this paper, we demonstrate on the InP substrate that this notion is not always sufficient to represent the injection dependence of the surface phenomena. The study of power dependence of TRPL decays coupled with modulated photoluminescence (MPL) spectra on four samples from the same wafer with different surface treatments (epi-ready, freshly cleaned, after air exposure, and with poly-phosphazen passivation) allows us to discriminate between bulk and surface properties. We introduce surface defect trapping as an alternative to explain TRPL decays and MPL phase excitation power dependences of the three non-passivated samples. Surface trap parameters such as capture cross section and defect density are extracted. The passivated sample exhibits an invariant response shape on eight orders of magnitude of illumination. The stability of the PL response at high flux is in agreement with the perfect stability of the passivation layer, which is able to protect the InP surface without chemical changes over more than one year. They are linked to the nature of the passivation layer/InP interface. Other surface treatments were found to have an injection dependent response at high flux corresponding to different surface defect distributions but also possibly to surface chemical changes for the freshly cleaned sample.

Characterization of InP Surfaces Perturbations after Ar+ Bombardment By Combining Electrochemistry and X-Ray Photoemission Spectroscopy

Over the past decades, the perturbations induced by ionic bombardment on semi-conductors have been explored, raising questions such as the deepness affected inside the material. Here, we focus on one well-known semi-conductor: InP, under Ar bombardment induced by an ionic sputtering performed directly inside the X-Ray photoemission spectroscopy (XPS) chamber using an ion gun. We already proved that, after a bombardment by Ar ions, InP surfaces suffer from several perturbations, degrading the initial properties of this semi-conductor: chemical ones (oxidation degree, atomic network organization and stoichiometry) [1], but also morphological and optical ones [2]... To get a better insight on the damages induced on the surfaces of InP semi-conductors, we present a study where electrochemistry is coupled to XPS analysis. Electrochemistry is indeed a very efficient probe to detect modification of the electrical and electrochemical properties of the materials but also a quantitative tool to provide information bulk and surface properties of any electrode material.In our approach, n- & p- type samples were investigated toward their modified electrochemical responses. We observed that, on p-type InP, after bombardment, the surface modification is evidenced by a lower dark open circuit potential compared to the one measured on pristine surface. Moreover, cyclic voltammetry performed at pH 10 shows initial cathodic features on the surface, related to an oxidized metallic In-enriched layer onto InP surface. This feature agrees with XPS analysis. By continuing the cyclic voltammetry, a more pronounced In rich overlayer formation is observed, due to specific oxidation /reduction phenomenon.[3] This behavior is very similar to the one obtained by cathodic decomposition onto InP surface. We will also explore the response of a n-type InP surface under similar conditions.In conclusion, we will discuss how the XPS and electrochemical characterizations combination is able to provide complete and complementary diagnostic of the stoichiometry loss and its electrochemical reactivity.[1] Aureau et al., SIA, 2018, 50 (11) 1163-1167 ; D. Aureau et al., ECS Trans., 2019, 89, 9[2] Béchu et al., JVST B, 2019, 27, 062902[3] Béchu et al., Electrochem. Comm., 2020, 117, 106766

Photoanodic oxidation of InP in acid solution and its surface chemistry: On the interplay of photons, protons and hydrodynamics

Factors determining etching and passivation of n-type InP in H2SO4 and HCl solution and the corresponding surface chemistry are considered. Passivation is favoured by higher light intensity and lower proton and Cl− ion concentration. Ex-situ surface analysis shows the passive (bi)layer to consist mainly of oxide-based In3+ and P5+ components: InPO4 and In(PO3)3. Hydrodynamics is found to play a decisive and surprizing role in determining the kinetics of the surface reactions. Oxygen-bridge formation between surface In and P atoms, as a result of deprotonation of a P-OH reaction intermediate, is considered to be important in determining competition between the two reaction paths: etching and passivation. These results are compared with markedly contrasting results for n-type GaAs under similar experimental conditions.

Broadband high quantum efficiency InGaAs/InP focal plane arrays via high precision plasma thinning.

We report on the fabrication of a 160×120 visible (Vis)-extended InGaAs/InP focal plane array (FPA) by means of the inductively coupled plasma etching. Compared to the conventional Vis-InGaAs FPAs, higher quantum efficiency in the Vis spectrum has been achieved. High precision thinning of the n-type InP contact layer down to 10 nm has led to quantum efficiencies higher than 60% over a broad wavelength range of 500-1700 nm. Benefiting from the textured surface after plasma etching, 17% lower reflectance over the entire response range was also found. Enhanced Vis/near-infrared (NIR) laboratory imaging capability has also been demonstrated, which has proved the feasibility of such processes for fabrication of future higher definition Vis/NIR InGaAs imagers.

Amorphous Gadolinium Aluminate as a Dielectric and Sulfur for Indium Phosphide Passivation

The passivation of n-type InP (100) using sulfur in combination with a gadolinium aluminate (GAO) dielectric layer has been studied. Photoluminescence, minority-carrier lifetime, and capacitance–voltage measurements indicate that a (NH4)2S vapor passivation step prior to atomic layer deposition of the oxide effectively lowers the interface state density. Surface and interface chemistry were studied by synchrotron radiation photoemission spectroscopy (SRPES). The effect of ex situ surface passivation after native oxide removal in HCl solution was examined. It was observed that surface reoxidation occurred during (NH4)2S vapor exposure, leading to the formation of Inx(HPO4)y. S was present on the surface as a sulfide in both surface and subsurface sites. After atomic layer deposition of GAO, sulfates were detected in addition to Inx(HPO4)y, which was confirmed by near-edge X-ray absorption fine structure analysis. The S in the stack was quantified using reference-free grazing incidence X-ray fluorescence an...

Fabrication and optical properties of InP/Cu2O nanojunctions

The InP/Cu2O nanojunction hybrid materials are fabricated by a facile method via electrodeposition of CU2O nanoparticles on the ordered one dimensional InP nanopore arrays. The morphology and element composition of the InP/Cu2O heterostructures are characterized. Experimental results indicate p-type Cu2O nanoparticles homogenously covered on the surface of n-type InP nanopore arrays and formed efficient heterogeneous structure. Compared to the pristine InP nanopore arrays, the InP/Cu2O nanoheterojunction structure have advantageous of the separation of photogenerated electron-hole pairs.

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In0.53Ga0.47As lattice matched to InP substrates

In this work, deep levels present in n-type In0.53Ga0.47As hetero-epitaxial layers grown lattice-matched on n-type InP substrates by molecular beam epitaxy have been studied by deep-level transient spectroscopy (DLTS). Metal–oxide–semiconductor capacitors are employed, based on an Al2O3 gate oxide. It is shown that a single, near mid-gap electron trap dominates the DLT-spectra, whatever the surface pre-or post-gate oxide deposition treatment. At the same time, it is shown that the deep level parameters vary significantly from capacitor to capacitor and from wafer to wafer. Only after Forming Gas Annealing, a stable value for the activation energy of 0.39 ± 0.01 eV is obtained. These results are tentatively interpreted in terms of antisite defects in the epitaxial layer, which form a family of related complexes with close deep-level parameters.

The Role of Misorientation in Direct Wafer Bonded III-V Materials

Direct wafer-bonding is a promising approach to materials integration for heterojunction structures not realizable through epitaxial means. Without lattice-parameter mismatch restrictions, wafer-bonding opens up a myriad of possibilities of materials combinations for many novel electronic device structures. In fact, wafer-bonding of III-V semiconductor materials was used to fabricate high-efficiency multijunction solar cells [1,2]. In this work, the effect of misorientation (both relative tilt and rotation) on the electronic properties across the bonded interface was studied by fabricating GaAs and InP homojunction and heterojunctions. To study the role of relative tilt, (001) n-type GaAs and (001) n-type InP wafers with offcut angles of 4° towards <111>A and nominal on-axis substrates were bonded to form relative tilts of 0°, 4°, and 8°. Current-voltage (I-V) curves were measured at various temperatures ranging from 90 K to 340 K to determine the interfacial barrier heights using the Seager and Pike electron model [3]. Then, to study the effect of rotation, (001) n-type InP wafers with twist angles ranging from 0° to 90° in 15° increments were bonded. Prior to bonding, the wafers were first cleaved into quarters and submerged in an NH4OH solution to remove the native surface oxide and then submerged in a 20% aqueous (NH4)2S solution for 5 minutes. After drying the wafers with N2, the wafers were brought face-to-face and very low pressure (kPa) was applied manually at room temperature and in ambient air pressure. The relative rotational misalignment was induced by rotating the top wafer prior to applying pressure. The wafers were then annealed at 400 °C for 2 hours to strengthen the bonded interface. Metal Ohmic contacts were deposited on each semiconductor surface and samples were diced into ~2 x 2 mm squares. We find that higher relative tilt across the interface leads to larger barrier heights. For example, in the GaAs/GaAs system the barrier height increased from 0.56 eV to 1.00 eV when increasing the tilt from 0° to 8°, respectively. Additionally, systems with at least one side InP (whether in an InP homojunction or InP/GaAs heterojunction) corresponded to lower barrier heights than the GaAs homojunction system. Regarding rotation, there is a discrepancy in literature on the effect of rotational misalignment. Kish et al. [4] claimed rotationally misaligning (001) III-V wafers by 20° and 90° result in the same decrease in electrical conductivity across the bonded interface compared to their 0° bonded wafers. However, Okuno et al. [5, 6] found that 0° and 90° bonded samples result in nearly equal electrical performance. Our findings show that the lowest interfacial resistance corresponded to misorientations of 0° and 90° while the greatest resistance corresponded to 45°, which was 30% higher than the lowest interfacial resistance. We conclude that the effect of rotational misalignment on the electrical conduction across bonded interfaces follows a sinusoidal pattern and its periodic effect on interfacial conductivity depends on the lattice symmetry of the wafer’s surface orientation, which has implications for bonding wafers with different surface symmetry. Electrical characterization of the interface enables us to understand the key factors that influence the properties of a bonded interface. We concluded that surface passivation, materials choice, and relative misorientation of the bonded materials are the determining factors that control the electrical performance of the bonded structure.

Model of Formation and Propagation of Nanoporous Structures in Indium Phosphide during Anodisation in Aqueous KOH

Porous layers are formed in highly doped (1018 cm-3) n-type InP anodised in concentrated aqueous KOH solutions. The pores have a characteristic diameter and propagate along <111>A directions. This preferential etching leads to porous regions with a characteristic tetrahedral shape. We have previously proposed a three-step mechanism of electrochemical pore formation: (1) hole generation at pore tips, (2) hole diffusion and (3) electrochemical oxidation of the semiconductor to form etch products. Step 1 determines the overall etch rate. However, if the kinetics of Step 3 are slow relative to Step 2, then etching can occur at preferred crystallographic sites leading to pore propagation in preferential directions. We have implemented the fundamental rules of this mechanism in a numerical simulation of this mechanism and we show that the simulation reproduces many of the features of pore growth in InP.

Terahertz excitation spectra of InP single crystals

Investigation of terahertz (THz) pulse generation from semi-insulating and n-type InP crystals surfaces is presented in this letter. In order to determine energy separation between the main and subsidiary conduction band valleys, THz pulse amplitude dependences on the photoexcitation wavelength (in a range of 410–950 nm) were measured. These dependences had a clear maximum at ∼540 nm, from which the inter-valley energy separation in the conduction band of InP as equal to 0.75 eV was determined. Moreover, THz generation mechanisms at laser excited surfaces of InP were investigated by additionally analyzing the azimuthal angle dependences of the emitted THz signal amplitude and power. It has been shown that the main physical mechanism of the surface THz emission in this material is the spatial separation of photoexcited electrons and holes, which can also lead to a symmetry similar to the second order optical nonlinearity. Photocurrent surge in the surface electric field can also contribute to the THz emission from a semi-insulating crystal illuminated by optical pulses with the wavelengths close to the absorption edge.

Microstructural, chemical states and electrical properties of Au/CuO/n-InP heterojunction with a cupric oxide interlayer

Cupric oxide (CuO) is synthesized by simple chemical bath deposition method and deposited on n-type InP substrate using e-beam evaporation technique. First, the structural and chemical compositional analysis of CuO/n-InP are analysed by X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS). XRD and XPS results confirmed that the formation of CuO on n-type InP substrate. Then, Au/CuO/n-InP heterojunction is fabricated with a CuO interlayer and correlated its results with the Au/n-InP Schottky junction (SJ). The barrier height (Φb) and ideality factor (n) are extracted through I-V and C-V methods and the respective values are 0.66 eV (I-V)/0.80 eV (C-V) and 1.24, and 0.78 eV (I-V)/0.94 eV (C-V) and 1.62 for the SJ and HJ diodes, respectively. By applying Cheung's and Norde functions, the Φb, ideality factor and series resistance (RS) are derived for the SJ and HJ diodes. The derived interface state density (NSS) of HJ is lower than the SJ; results demonstrated that the CuO interlayer plays an important role in the decreased NSS. The Poole-Frenkel emission is the dominant current conduction mechanism in reverse bias of both SJ and HJ diodes.

Electrical and optical performances of InGaAs/GaAsSb superlattice short-wavelength infrared detectors

We report on a p-i-n photodetector based on type II InGaAs/GaAsSb SLs with a cutoff wavelength of 2.5 μm at room temperature. High quality materials were grown on an n-type (100) InP substrate by molecular beam epitaxy. Photoluminescence spectroscopy peak of the SLs around 2.5 μm and atomic steps in the atomic force microscope image were clearly observed. A device with the 100% cutoff wavelength of 2.5 μm at 293 K was fabricated. Temperature-dependent current-voltage measurements show that the diffusion current and generation-recombination current dominate at temperatures higher than 200 K while the generation-recombination current and trap-assisted tunneling current dominate at temperatures below 200 K. The optical response measurement quantum efficiency increases with reverse bias, and a diffusion length of 0.3 μm was extracted. The cause of the small diffusion length and possible approaches to improve it were briefly discussed.

Surface morphological, electrical and transport properties of rapidly annealed double layers Ru/Cr Schottky structure on n-type InP

The electrical and transport properties of a fabricated bilayer Ru/Cr/n-InP Schottky diode (SD) have been investigated at different annealing temperatures. Atomic force microscopy results have showed that the overall surface morphology of the Ru/Cr/n-InP SD is fairly smooth at elevated temperatures. High barrier height is achieved for the diode annealed at 300 °C compared to the as-deposited, annealed at 200 and 400 °C diodes. The series resistance and shunt resistance of the Ru/Cr/n-InP SD are estimated by current–voltage method at different annealing temperatures. The barrier heights and series resistance are also determined by Cheung’s and modified Norde functions. The interface state density of the Ru/Cr/n-InP SD is found to be decreased after annealing at 300 °C and then slightly increased upon annealing at 400 °C. The difference between barrier heights obtained from current–voltage and capacitance–voltage is also discussed. Experimental results have showed that the Poole–Frenkel emission is found to be dominant in the lower bias region whereas Schottky emission is dominant in the higher bias region for the Ru/Cr/n-InP SDs irrespective of annealing temperatures.

Au/n-InP Schottky diodes using an Al2O3 interfacial layer grown by atomic layer deposition

We investigated the effect of an Al2O3 interfacial layer grown by atomic layer deposition on the electrical properties of Au Schottky contacts to n-type InP. Considering barrier inhomogeneity, modified Richardson plots yielded a Richardson constant of 8.4 and 7.5 Acm−2K−2, respectively, for the sample with and without the Al2O3 interlayer (theoretical value of 9.4 Acm−2K−2 for n-type InP). The dominant reverse current flow for the sample with an Al2O3 interlayer was found to be Poole–Frenkel emission. From capacitance–voltage measurements, it was observed that the capacitance for the sample without the Al2O3 interlayer was frequency dependent. Sputter-induced defects as well as structural defects were passivated effectively with an Al2O3 interlayer.

Effects of high-k zirconium oxide (ZrO2) interlayer on the electrical and transport properties of Au/n-type InP Schottky diode

The structural, chemical, electrical and carrier transport properties of high-k ZrO2 on n-type InP with Au electrode have been studied by X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS), current-voltage (IV) and capacitance-voltage (CV) techniques at room temperature. Results show that the high barrier height is achieved for the Au/ZrO2/n-InP metal-insulator-semiconductor (MIS) diode as compared to the Au/n-InP metal-semiconductor (MS) diode. Using Cheung's functions, the barrier height, ideality factor and series resistance are estimated for the MS and MIS diodes. The barrier heights are determined by IV, Cheung's and surface potential-forward voltage plot for both the MS and MIS diodes which are found to be in good agreement with each other. Results indicate that the interface state density of Au/ZrO2/n-InP MIS diode is lower than that of Au/n-InP MS diode. This may be attributed to the fact that the introduction of the high-k ZrO2 interlayer led to reduction of the interface state density in the Au/n-InP MS diode. Results indicate that the Poole-Frenkel emission is the dominant conduction mechanism in the lower bias region while Schottky emission is dominant in the higher bias region for both the Au/n-InP MS and Au/ZrO2/n-InP MIS diodes.

Electrochemical Pore Formation in InP: Understanding and Controlling Pore Morphology

Research on semiconductor nanostructures is motivated by two key considerations. The first is the continuing call for smaller and more efficient versions of existing semiconductor devices. The second is the characterisation and exploitation of the unique characteristics that are often exhibited by structures at the nano-scale. While a wide variety of semiconductor nanostructures can be produced without difficulty (e.g. by self-assembly or preferential etching), precise control over the morphology of these structures is often much harder to achieve. The electrochemical formation of nano-scale porosity in semiconductors has been studied extensively1-5 and has found some application due to its bulk characteristics e.g. the use of porous silicon as a passivation layer6. However, the exploitation of the nano-scale properties of these structures is unlikely until a comprehensive understanding of the factors affecting pore morphology has been obtained. We have previously demonstrated7-9 the formation of nano-scale porosity in n-type InP anodised in KOH. Pores emerge form pits in the electrode surface10 and grow and branch along the <111>A crystallographic directions9 forming tetrahedral porous domains8. Under certain conditions, current-line oriented pores can also be obtained.11 In order to understand the factors effecting pore morphology, porous InP was formed under a range of different temperatures, electrolyte concentrations, carrier concentrations and current densities. The morphology of the resulting porous layers was analysed in detail. In particular, the pore width, layer thickness and porosity of the layers were all measured. We show that at low current densities, the pore width is dominated by the magnitude of the current density. At higher current densities, we show that both the pore width and the porosity are inversely related to the kinetics of the electrochemical reaction: the pore width being lowest at high temperatures and intermediate KOH concentrations. The pore width decreases with increasing carrier concentration, which is likely due to the associated decrease in the space charge layer thickness. Porosity varies in a similar manner to pore width and the maximum porous layer thickness is correlated to the pore width in all cases. These results support a model9of pore formation based on competition in kinetics between hole supply at the pore tip and the electrochemical reaction at the semiconductor electrolyte interface. It will be shown that this model makes the correct qualitative predictions for the variation of pore morphology with temperature, electrolyte concentration, carrier concentration and current density. Such an understanding of the factors affecting the morphology of these porous layers is an essential step in achieving the process control necessary for them to be integrated into standard semiconductor fabrication techniques.