N-drift Region Research Articles

High breakdown single-crystal GaN p-n diodes by molecular beam epitaxy

Molecular beam epitaxy grown GaN p-n vertical diodes are demonstrated on single-crystal GaN substrates. A low leakage current <3 nA/cm2 is obtained with reverse bias voltage up to −20 V. With a 400 nm thick n-drift region, an on-resistance of 0.23 mΩ cm2 is achieved, with a breakdown voltage corresponding to a peak electric field of ∼3.1 MV/cm in GaN. Single-crystal GaN substrates with very low dislocation densities enable the low leakage current and the high breakdown field in the diodes, showing significant potential for MBE growth to attain near-intrinsic performance when the density of dislocations is low.

A novel low turnoff loss carrier stored SOI LIGBT with trench gate barrier

A novel low turnoff loss carrier stored (CS) silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with trench gate barrier (CS SOI TGLIGBT) is proposed. The proposed CS SOI TGLIGBT features a trench gate inserted between the pwell and n-drift. Firstly, the trench gate acts as a hole barrier to prevent the hole from injecting directly into pwell in the on-state, which introduces carrier stored effect and realizes a uniform carriers distribution in the n-drift region, resulting in a decrease of the on-state voltage drop (Von). Secondly, due to the carrier stored effect and the assisted depleted effect induced by the trench gate, large number of carriers can be quickly removed at the initial turnoff process, leading to a decrease of turnoff loss (Eoff). The influences of gate trench barrier on Von and Eoff are investigated. Simulation results show that the proposed CS SOI TGLIGBT can achieve a 59% lower Eoff compared with the conventional SOI trench gate LIGBT at the same Von of 1.15 V.

Advanced hexagonal layout design for split‐gate reduced surface field stepped oxide U‐groove metal–oxide–semiconductor field‐effect transistor

Split-gate reduced surface field (RESURF) stepped oxide (SGRSO) device with advanced hexagonal p-pillar (AHP) layout is investigated using three-dimensional simulations. The AHP layout can improve the on-state characteristics while not increasing the process difficulty. The p-pillar under the source electrode enhances the RESURF effect to the n-drift region, so that the n-drift region doping concentration could be substantially increased and the breakdown voltage is not reduced. Based on the SGRSO device, the AHP layout modifies the electric field distribution in the n-drift region, and reduces the RSP as compared with the common hexagonal and mesa strip layout structures. The figure of merit of the AHP layout improves by 49.8% as compared with the other two types of layouts, and the AHP has superior characteristics within a wider ND range.

An Ultra-Low Specific ON-Resistance LDMOST With Self-Driven Split Gate

An n-Laterally Double Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOST) with self-driven split p-top gate is studied. By integrating a low-voltage charge pump circuit, a constant positive voltage (≈10 V) is self-generated in the OFF-state and applied to the split p-top electrode in the ON-state. This voltage assists the accumulation of electrons near the surface of the n-drift region. As a result, the specific ONresistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is reduced without an increase in effective gate charge Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> . Moreover, the adaptation of the optimum variation lateral doping enables a shorter n-drift region length to support the same breakdown voltage. The simulation results indicate that for a 600 V device, the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 20.7 mQ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This is approximately five times smaller than a conventional double REduced SURface Field LDMOST.

A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P+ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P+ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P+ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405V from 84V of the conventional LDMOS on 1µm silicon layer and 2µm buried oxide layer. Also, effective values of doping, length, and depth of P+ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.

Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron, sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.

DC Characteristics Optimization of a Double G-Shield 50 V RF LDMOS

An N-type 50 V RF LDMOS with a RESURF (reduced surface field) structure of dual field plates (grounded shield, or G-shield) was investigated. The effect of the two field plates and N-drift region, including the junction depth and dopant concentration, on the DC characteristics was analyzed by employing the Taurus TCAD device simulator. A high BV (breakdown voltage) can be achieved while keeping a lowRDSON(on-resistance). The simulation results show that the N-drift region dopant concentration has an obvious effect on the BV andRDSONand the junction depth affected these values less. There is an optimized length for the second field plate for a given dopant concentration of the N-drift region. Both factors should be optimized together to determine the best DC characteristics. Meanwhile, the effect of the first field plate on the BV andRDSONcan be ignored. According to the simulation results, 50 V RF LDMOS with an optimized RESURF structure of a double G-shield was fabricated using 0.35 µm technologies. The measurement data show the same trend as the TCAD simulation, where a BV of 118 V andRDSONof 26 ohm·mm were achieved.

Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage

A novel Lateral Double-diffusion Metal Oxide Semiconductor (LDMOS) is proposed to enhance its breakdown voltage (BV) and reduce specific ON-resistance (RON,sp), and its mechanism is investigated by simulation. It features a junction field plate (JFP) at surface and an N+ floating layer (NFL) in the P-substrate. The lateral variation doping JFP not only modulates the surface electric field (E-field) distribution to improve the BV, but also allows a high N-drift doping concentration and thus reduces the RON,sp owing to the charge compensation effect between the N-drift region and P region in the JFP in the OFF-state. The heavily doped NFL is not fully depleted and thus is an equipotential layer in the lateral direction. It thus reshapes the equipotential contours at both the source and drain sides, avoiding the E-field concentration and premature breakdown under the drain; moreover, the additional vertical diode is induced between the NFL and P-sub and it thus extends the depletion width in P-sub, both of which increase the BV. The RON,sp and BV of the JFP-NFL LDMOS is improved by 47% and 63%, respectively, compared with those of a conventional LDMOS at the same dimension. The JFP-NFL LDMOS achieves a superior tradeoff between RON,sp and BV to the different single-, double-, and triple-REduced SURface Field LDMOSFETs with planar technology.

Way of operation to improve performance for advanced split‐gate resurf stepped oxide UMOSFET

In this study, a way of operating a double split-gate resurf stepped oxide (DSGRSO) UMOS has been proposed. The n-drift region is divided into two parts by the double split-gate: the upper one and the lower one, which enhances the resurf active effect and binges in an electric field peak in the middle of the n-drift region, and decreases the width of split-gate trench, resulting in an increase of figure of merit (FOM). The simulation results show that the DSGRSO UMOS has improved the saturated breakdown voltage by 25.7% and FOM by 108% as compared with SGRSO UMOS at the certain aspect ratio.

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal—oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (Ron.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in Ron.sp by 45.7% simultaneously.

Extended Trench Gate Superjunction Lateral Power MOSFET for Ultra-Low Specific on-Resistance and High Breakdown Voltage

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in and a 16% improvement in BV.

Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80μm, the NBL PSOI LDMOS obtains a high BV of 1243V which is improved by around 105V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333K at a power (P) of 1mW/μm which is reduced by around 61K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

고내압 SiC-IGBT 소자 소형화에 관한 연구

Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (∼2.3 MV/cm), and high bulk electron mobility (∼900 cm 2 /Vs). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage (VB= 1,600 V), lower on-resistance (Ron= 0.43 mΩ·cm 2 ) than Si-IGBT. Also, we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V.

High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

In this paper, a split-gate resurf stepped oxide (RSO) vertical UMOSFET with p-pillar under the p+ plug region structure is proposed. The p-pillar could modulate the electric field of the drift region with the split-gate in 3-D and simultaneously brings electric field peaks at the sidewall junction between p-pillar and n-drift region. Thus the split-gate enhanced with p-pillar (SGEP) UMOS could increase the drift region doping concentration, reduce the on-state-specific resistance, and maintains the breakdown voltage as compared with the super junction and split-gate RSO UMOSs. Numerical simulation results show that the charge imbalance endurance of SGEP is also largely increased.

Kirk effect and suppression for 20 V planar active-gap LDMOS

For 20 V planar active-gap lateral double-diffused MOSFET (LDMOS), the sectional channel is utilized to decrease the electric field in the n-drift region below the poly gate edge in the off-state, compared with the conventional single channel. Then the n-drift concentration can be increased to decrease the Kirk effect, while keeping off-state breakdown voltage Vbd unchanged. Meanwhile the influence of the n-drift concentration and the n-drift length Ldrift (the drain n+ diffusion to gate spacing) which are related to the Kirk effect is discussed. The trade-offs between Rdson·Area, breakdown voltage Vbd and the electrical safe operating area (e-SOA) performance of LDMOS are considered also. Finally the proposed planar active-gap LDMOS devices with varied values of Ldrift are experimentally demonstrated. The experimental results show that the Kirk effect can be greatly suppressed with slight increase in the Rdson·Area parameter.

Ultra-low specific on-resistance vertical double-diffused metal—oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench (HK TG VDMOS) is proposed in this paper. The HK TG VDMOS features a high-k (HK) trench below the trench gate. Firstly, the extended HK trench not only causes an assistant depletion of the n-drift region, but also optimizes the electric field, which therefore reduces Ron,sp and increases the breakdown voltage (BV). Secondly, the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration. Thirdly, compared with the superjunction (SJ) vertical double-diffused metal-oxide semiconductor (VDMOS), the new device is simplified in fabrication by etching and filling the extended trench. The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation; its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%, in comparison with those of the conventional trench gate VDMOS (TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).

Band-to-Band Tunneling Injection Insulated-Gate Bipolar Transistor with a Soft Reverse-Recovery Built-In Diode

A band-to-band tunneling injection insulated-gate bipolar transistor (IGBT) featuring a tunnel junction as the collector p-n junction is proposed. The tunnel junction injects not only holes into the n-drift region by diffusion when it is forward biased but also electrons by band-to-band tunneling when it is reverse biased. Thus, the proposed device shows the output characteristics of a reverse conducting IGBT (RC-IGBT). Compared with the conventional RC-IGBT, which is prone to current concentration, the proposed device conducts current uniformly in both forward and reverse conducting states, which are favorable to the increase in conducting capability and the reduction in the reverse recovery peak current. During the reverse recovery, the electrons extracted from the drift region to the collector induce the hole injection into the drift region, which leads to the soft reverse recovery of the built-in diode. In addition, the technological ease of fabrication (no backside photolithography) is another attraction of the proposed device.

Semi-quantitative analysis of the depth distribution of radiative recombination centers in silicon power devices by cross-sectional cathodoluminescence

A procedure to obtain the semi-quantitative depth distribution of radiative recombination centers in silicon power devices has been developed using cross-sectional cathodoluminescence (CL) by considering the nonradiative recombination on the surface of devices. Sharp luminescent peaks at 1.018 eV (W or I1), 1.040 eV (X or I3), and 0.790 eV (C) and a broad band about 0.90–1.05 eV in addition to near-band-edge emission were observed in the n-drift layer of the electron-irradiated lifetime-controlled punch-through insulated gate bipolar transistors using cross-sectional CL measurements. The semi-quantitative depth distributions of X, W, and C centers were obtained by the procedure. Each had a maximum value at the midpoint of the n-drift region, although electrons conventionally used to control carrier lifetime in power devices penetrated the entire device. One of the possible mechanisms for these distributions is the interaction of the X, W, and C centers with other point-like defects and impurities near the surface and the interface. The minority carrier (hole) diffusion length and the reduced recombination velocity in the devices are also extracted by this procedure.