N-channel Tunnel Field-effect Transistors Research Articles

Impact of Fringing Field on Shell Radius and Spacer Dielectric on Device Performance of InAs-GaSb Core-Shell Nanowire nTFET

A comprehensive investigation with the help of 3D device simulation, we demonstrate the impact of fringing field on shell radius of InAs-GaSb core–shell nanowire n-channel tunnel field effect transistor (TFET) in this paper. Increase in shell radius intensifies the magnitude of fringing electric field towards shell region. This results in generation of depletion zone in the shell near the gate edge affects the device performance metrics such as on current and threshold voltage. It is demonstrated that by appropriate gate engineering the influence of fringing electric field can be circumvent. High-k spacer dielectric at the gate underlap shows improvement in device performance metrics such as on current with sub subthreshold swing. An investigation of the effect of drain voltage on the device characteristics exhibits the privation of tunneling resistance limited region. Furthermore, the output characteristics for such an architecture bear a resemblance to long channel MOSFET (metal oxide semiconductor field effect transistor).

Label Free DNA Detection Techniques Using Dielectric Modulated FET: Inversion or Tunneling?

In this paper, a feasibility estimation of inversion and tunneling based n-type dielectric modulated transistor has been extensively carried out for label free DNA detection. The sensing ability of the devices are investigated based on shift in threshold voltage and on-current ($I_{on}$ ) with respect to change in permittivity, angle of orientation, and negative charge density of DNA biomolecules. The investigation results show that n-channel Tunneling Field Effect Transistor (TFET) has better sensing capability than n-channel Inversion Mode Field Effect Transistor (IMFET) without compromising on scaling issues. When DNA biomolecules are anchored in the nanogap region, the n-channel IMFET exhibits the shift in threshold voltage and adequate sensitivity. However, it requires a high gate bias to detect the biomolecule. In the case of n-channel TFET, steep subthreshold swing with high $I_{on}$ is observed at low gate bias. Consequently, the sensitivity of TFET is enhanced by 63% when compared with IMFET. This results show TFET devices are superior and can replace the existing IMFET with cost effectiveness. The design and comparative evaluation of the devices are carried out with 2D Silvaco TCAD.

GeSn/GeSiSn double-heterojunction short channel tunnel field-effect transistor design

The traditional GeSn/GeSiSn single-heterojunction (SH) n-channel tunneling field-effect transistor (NTFET) faces a serious off-state current (IOFF) breakdown and a subthreshold swing (SS) degradation when the channel length is scaled to 10 nm. In this work, we propose a double-heterojunction (DH) short channel NTFET by utilizing heterojunction engineering. A 60% lower IOFF value (4.83 × 10−10 A μm−1), a 6.2 times higher ION value (9.39 × 10−6 A μm−1) and an SS of 39.14 mV/dec are achieved in the DH NTFET at 0.3 V compared to the SH NTFET when the channel length is 10 nm.

Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field

In this work, the accuracy of a compact current–voltage (I–V) model for double-gate n-channel tunnel field-effect transistors (TFETs) is improve by considering outer and inner gate fringing field effects. The refined model is benchmarked against technology computer-aided design (TCAD) device simulations and compared against a previously published compact model. The normalized root-mean-square error for current in the linear region of operation (i.e., for 0.05 V drain voltage) is reduced from ∼593 to ∼5%.

A comprehensive investigation of silicon film thickness (TSI) of nanoscale DG TFET for low power applications

In this work we demonstrate an N-channel tunnel field effect transistor (TFET) i.e. double gate N-TFET for improved subthreshold slope (SS) and OFF-state leakage current (IOFF) with reference to drain bias (VDS), and body thickness (TSI). Device thickness is becoming a crucial parameter as more devices can built on thin film and integrate double or multi-gate MOSFETs. In this model we analyze the impact of VDS and TSI on the device performances and express the limitation of TSI with respect to ON-state current (ION), electric field, energy band diagram, etc. TFETs have become popular because these devices can operate in the sub-threshold region with the larger transconductance to current ratio (gm/Id) than MOSFETs, the current turn-on mechanism being interband tunneling rather than thermionic emission. The proposed model can achieve a subthreshold swing less than 35 mV/decade that is desirable for designing low-power high-frequency analog integrated digital circuit applications.

Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC’s). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

Dielectric engineered symmetric underlap double gate tunnel FET (DGTFET): An investigation towards variation of dielectric materials

In this article, an underlap silicon n-channel Tunnel Field Effect Transistor (n-TFET) i.e., symmetric single-k spacer (SSS) Double Gate N-TFET (DGTFET) is proposed to improve the performance of the device by using different spacer materials. A detailed investigation has been made on the proposed device characteristics with the help of extensive 2-D TCAD simulations. It is demonstrated that an optimized underlap length is chosen for a significant on-state current (Ion) without deteriorating the off-state current (Ioff) and sub-threshold swing (SS). The proposed model with different spacer materials has been extensively analyzed by using transfer characteristics, output characteristics, and analog/RF characteristics. The structure is optimized based on the comparison among various performance metrics like Ion, Ioff, SS, on-off ratio (Ion/Ioff), threshold (or) cut-off frequency (fT), and intrinsic delay with considering different spacer materials like SiO2 (k = 3.9), Si3N4 (k = 7.5), and HfO2 (k = 25).

Investigation of performance enhancement in InAs/InGaAs heterojunction-enhanced N-channel tunneling field-effect transistor

We design a heterojunction-enhanced n-channel tunneling field effect transistor (HE-TFET) with an InAs/In1−xGaxAs heterojunction located in channel region with a distance of LT-H from source/channel tunneling junction. The influence of LT-H on the performance of HE-TFETs is investigated by simulation. Compared with InAs homo-NTFET, the positive shift of onset voltage, the steeper subthreshold swing (SS), and the enhanced on-state current ION are achieved in HE-NTFETs, which is attributed to the modulation of the heterojunction on band-to-band tunneling. At a supply voltage of 0.3 V, ION of InAs/In0.9Ga0.1As HE-NTFET with a LT-H of 6 nm demonstrates an enhancement of 119.3% in comparison with the homo device. Furthermore, the impact of Ga composition on the performance of HE-NTFETs is studied. As the Ga composition increases, the average SS characteristics of HE-NTFETs are improved, while the drive current of devices is reduced due to the increasing of tunneling barrier.

Band-Offset Engineering for GeSn-SiGeSn Hetero Tunnel FETs and the Role of Strain

In this paper a simulation study of the effect of conduction and valence band offsets on the subthreshold swing (SS) of a double-gate tunnel field-effect transistor (TFET) with gate-overlapped source is presented. The simulations show that if the pn-junction and the hetero-junction coincide, the band offsets can significantly improve the SS by suppressing the so-called point tunneling at the pn-junction. It turns out that the performance of an n-channel TFET is determined by the direct conduction band offset whereas that of a p-channel TFET is mainly effected by the energy difference between the light hole bands of the two materials. Thus, the performance of the hetero-junction TFET can be improved by selecting material systems with high conduction or valence band offsets. The misalignment between the pn-junction and the hetero-junction is shown to degrade the SS. The above-described band-offset engineering has been applied to the GeSn/SiGeSn hetero-structure system with and without strain. Simulations of GeSn/SiGeSn hetero-TFETs with band-to-band-tunneling parameters determined from pseudopotential calculations show that compressive strain in GeSn widens the design space for TFET application while tensile strain reduces it.

(Invited) Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs

The Tunnel Field Effect Transistor (TFET) which utilizes the band-to-band-tunneling (BTBT) generation current of a gated diode is regarded as promising candidate for ultra-low power circuits. TFETs with different geometries and operation modes have been proposed. In this work, we study different hetero-structure systems - InAs/Si and all-III-V (In0.53Ga0.47As/InP, InAs/GaSb) - and compare their performance in TFET applications. First, we evaluate the TCAD model by simulating realistic structures as the one shown in Fig. 1 and compare the results with measured current-voltage (IV) characteristics. Then we focus on 2D double-gate TFETs with gate-overlapped-source geometry (Fig. 2) which capture the essential physics. The TEM image of an InAs/Si nanowire p-TFET fabricated at IBM Research-Zurich is shown in Fig. 1. The n-doped InAs source (ND=2e18cm-3) is overlapped with the gate to increase “line” (under-the-gate) tunneling. Geometry and doping profile of a p-TFET used for the simulations are displayed in Fig. 2(a). The source donor concentration is at its optimum for minimum sub-threshold swing (SS), the corresponding value for the In0.53Ga0.47As/InP p-TFET being ND=1e19cm-3. The distributions of the electron and hole BTBT generation rates in the sub-threshold regime are shown in Fig. 2(b) and Fig. 2(c) for both material systems. One observes that BTBT takes place along the line tunnel path in the In0.53Ga0.47As/InP TFET while it occurs primarily along a “point” tunnel path (in-junction, inter-material) in the InAs/Si TFET. This is a result of the opposite signs of the valence band offset in the two hetero-systems. The different dominant tunnel paths result in different transfer characteristics as shown in Fig. 3. In bulk-like devices, the point tunneling rate is expected to change less rapidly than the line tunneling rate. Hence, the SS (averaged over 3 decades above 1e-9A/µm) of the InGaAs/InP TFET is slightly smaller than that of the InAs/Si TFET (47.3 vs 48.5). The difference is more pronounced in n-channel TFETs formed with the same set of hetero-systems. Also the current I60 (ID@ SS=60mV/dec) is comparable (6e-9A/µm vs 2e-9A/µm). In the simulations, the effect of the diffusion barrier of the InGaAs/InP hetero-system has been minimized by a proper composition gradient. In addition to the above effects, the quality of the interfaces will affect the IV characteristics. The lattice-matched In0.53Ga0.47As/InP interface is expected to exhibit a lower trap density than the highly mismatched InAs/Si interface. We will demonstrate the effect of trap-assisted tunneling on the TFET performance. Figure 1

Can p-channel tunnel field-effect transistors perform as good as n-channel?

We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10× smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration.

Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al2O3-based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125mV/dec and lower ION/IOFF ratio of 103–104 were obtained. It is expected that these device characteristics can be improved by further process optimization.

Strained-Si/strained-Ge type-II staggered heterojunction gate-normal-tunneling field-effect transistor

A SiGe-based n-channel tunnel field-effect transistor design employing a strained-Si/strained-Ge staggered-gap heterojunction with a small effective band-gap (122 meV) at the interface is investigated via numerical simulations using a semi-classical quantum correction obtained from the density-gradient model. A gate-normal tunneling geometry is used to increase tunneling area and reduce subthreshold swing. The strain leads to degeneracy breaking among the silicon conduction band valleys, reducing the density of states and associated quantum capacitance with better gate-to-tunnel barrier coupling. Performance evaluation using a figure-of-merit “I60,” where the drain current corresponds to a subthreshold slope of 60 mV/decade, suggests that the device has the potential to be competitive with modern metal-oxide-semiconductor field-effect transistors.

A Silicon Tunnel Field-Effect Transistor with an In Situ Doped Single Crystalline Ge Source for Achieving Sub-60 mV/decade Subthreshold Swing

We report the demonstration of an n-channel lateral Si tunnel field-effect transistor (TFET) with a single crystalline Ge source fabricated using the gate-last process. The p+ Ge source was in situ doped and grown at 320°C. An abrupt interface between Ge source and Si channel with type-II band alignment and a steep source doping profile (∼1.5 nm/decade) formed the tunneling junction. This allows the realization of a TFET with a steep subthreshold swing of 49 mV/decade at room temperature and an ION/IOFF ratio of 107.

Band offset determination of mixed As/Sb type-II staggered gap heterostructure for n-channel tunnel field effect transistor application

The experimental study of the valence band offset (ΔEv) of a mixed As/Sb type-II staggered gap GaAs0.35Sb0.65/In0.7Ga0.3As heterostructure used as source/channel junction of n-channel tunnel field effect transistor (TFET) grown by molecular beam epitaxy was investigated by x-ray photoelectron spectroscopy (XPS). Cross-sectional transmission electron micrograph shows high crystalline quality at the source/channel heterointerface. XPS results demonstrate a ΔEv of 0.39 ± 0.05 eV at the GaAs0.35Sb0.65/In0.7Ga0.3As heterointerface. The conduction band offset was calculated to be ∼0.49 eV using the band gap values of source and channel materials and the measured valence band offset. An effective tunneling barrier height of 0.21 eV was extracted, suggesting a great promise for designing a metamorphic mixed As/Sb type-II staggered gap TFET device structure for low-power logic applications.

Defect assistant band alignment transition from staggered to broken gap in mixed As/Sb tunnel field effect transistor heterostructure

The compositional dependence of effective tunneling barrier height (Ebeff) and defect assisted band alignment transition from staggered gap to broken gap in GaAsSb/InGaAs n-channel tunnel field effect transistor (TFET) structures were demonstrated by x-ray photoelectron spectroscopy (XPS). High-resolution x-ray diffraction measurements revealed that the active layers are internally lattice matched. The evolution of defect properties was evaluated using cross-sectional transmission electron microscopy. The defect density at the source/channel heterointerface was controlled by changing the interface properties during growth. By increasing indium (In) and antimony (Sb) alloy compositions from 65% to 70% in InxGa1−xAs and 60% to 65% in GaAs1−ySby layers, the Ebeff was reduced from 0.30 eV to 0.21 eV, respectively, with the low defect density at the source/channel heterointerface. The transfer characteristics of the fabricated TFET device with an Ebeff of 0.21 eV show 2× improvement in ON-state current compared to the device with Ebeff of 0.30 eV. On contrary, the value of Ebeff was decreased from 0.21 eV to −0.03 eV due to the presence of high defect density at the GaAs0.35Sb0.65/In0.7Ga0.3As heterointerface. As a result, the band alignment was converted from staggered gap to broken gap, which leads to 4 orders of magnitude increase in OFF-state leakage current. Therefore, a high quality source/channel interface with a properly selected Ebeff and well maintained low defect density is necessary to obtain both high ON-state current and low OFF-state leakage in a mixed As/Sb TFET structure for high-performance and lower-power logic applications.

InGaAs/InP Tunnel FETs With a Subthreshold Swing of 93 mV/dec and $I_{\rm ON}/I_{\rm OFF}$ Ratio Near $\hbox{10}^{6}$

Vertical n-channel tunnel field-effect transistors (TFETs) with tunneling normal to the gate based on an n+ In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞=0.53-&gt;;1</sub> GaAs/p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> InP heterojunction have been demonstrated to exhibit simultaneously a high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , a minimum subthreshold swing (SS) of 93 mV/dec, and an on-current of 20 μA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V and a gate swing of 1.75 V at 300 K, a record TFET performance. The significant improvement in device performance is ascribed to the adoption of a thin equivalent oxide thickness (EOT) of ~1.3 nm for improved electrostatics and the use of plasma-enhanced chemical vapor deposition SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞</sub> mesa passivation to preserve the integrity of the thin exposed semiconductor layers.

Performance of AlGaSb/InAs TFETs With Gate Electric Field and Tunneling Direction Aligned

The current-voltage characteristics of AlGaSb/InAs staggered-gap n-channel tunnel field-effect transistors are simulated in a geometry in which the gate electric field is oriented to be in the same direction as the tunnel junction internal field. It is shown that this geometry can also support low-voltage operation and low subthreshold swing. In the absence of a simple analytic theory for this transistor to allow direct analytic comparisons, two-dimensional numerical simulations are used to explore the electrostatic and geometrical design considerations including dependence on gate length, gate underlap, gate undercut, and equivalent oxide thickness.

Vertical InGaAs/InP Tunnel FETs With Tunneling Normal to the Gate

Vertical n-channel tunnel field-effect transistors (FETs) based on compound semiconductors, in a new geometry with tunneling normal to the gate, are demonstrated for the first time using an n+ In0.53Ga0.47As/n+ /n+,=0.53- >;1 GaAs/p+ InP heterojunction. At 300 K, the TFETs show an on-current of ~20 μA/μm and a minimum subthreshold swing (SS) of 130 mV/dec using an Al2O3 gate dielectric (EOT ~3.4 nm). Postdeposition annealing of the gate dielectric improves SS, and device passivation using atomic layer deposition can effectively prevent degradation of drain current over time. The clear negative differential resistance (NDR) observed in the tunnel junction and the trend toward NDR in the TFETs confirm that the transport mechanism in these FETs is interband tunneling.

SPICE Behavioral Model of the Tunneling Field-Effect Transistor for Circuit Simulation

The tunneling field-effect transistor (TFET) is an alternative device for deep-submicrometer CMOS with very good short channel and leakage characteristics. In this brief, a SPICE behavioral model that well captures the I- V characteristics and the parasitic capacitance of the n-channel TFET is proposed to facilitate efficient circuit design and simulation. The validity of the model is verified with technology computer-aided design (TCAD) simulation. The accuracy is within 10% and is of an order of magnitude faster than the TCAD.