Abstract
The tunneling field-effect transistor (TFET) is an alternative device for deep-submicrometer CMOS with very good short channel and leakage characteristics. In this brief, a SPICE behavioral model that well captures the I- V characteristics and the parasitic capacitance of the n-channel TFET is proposed to facilitate efficient circuit design and simulation. The validity of the model is verified with technology computer-aided design (TCAD) simulation. The accuracy is within 10% and is of an order of magnitude faster than the TCAD.
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