Mum Bulk CMOS Research Articles

An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process

This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 mum CMOS technologies show good accuracy (error ~5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 mum bulk CMOS technology and measured to demonstrate the operation of the test structure.

True Random Number Generator With a Metastability-Based Quality Control

We present a metastability-based true random number generator that achieves high entropy and passes NIST randomness tests. The generator grades the probability of randomness regardless of the output bit value by measuring the metastable resolution time. The system determines the original random noise level at the time of metastability and tunes itself to achieve a high probability of randomness. Dynamic control enables the system to respond to deterministic noise and a qualifier module grades the individual metastable events to produce a high-entropy random bit-stream. The grading module allows the user to trade off output bit-rate with the quality of the bit-stream. A fully integrated true random number generator was fabricated in a 0.13 mum bulk CMOS technology with an area of 0.145 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Radiation Hardened by Design Register File With Lightweight Error Detection and Correction

A radiation hardened by design 32times36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 mum bulk CMOS process with a measured speed over 1 GHz at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.

An Area and Power Efficient Radiation Hardened by Design Flip-Flop

A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> /mg) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described