Abstract
A radiation hardened by design 32times36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 mum bulk CMOS process with a measured speed over 1 GHz at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.
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