Research and implemention of interleaving grouping Hamming code algorithm

Abstract

For the space application, single event upset (SEU) is one of the important causes of fault or even failure of system on chip (SOC), the error detection and correction (EDAC) technique is often adopted to protect memory cells in SOC against SEU error. To improve the EDAC ability and to decrease the area overhead of storing check-bits, a interleaving grouping Hamming code algorithm about 32-bit data is proposed. Each 32-bit data are divided crosswise into 2 groups, each group adopts a single error correction and double error detection (SEC-DED) (22, 16) Hamming code, and the check-bits are interleaved storage. The number of the check-bits is only two thirds of that of the double error correction and four error detection Bose-Claudhuri-Hocquenghem (BCH) code. The proposed method can correct all burst 2-bit error, and can detect all burst no greater than 5-bit error, otherwise, part 3-bit to 24-bit faults can be also detected. The concrete encoder and decoder are implemented, and a greedy algorithm is developed to minimize hardware area overhead. The 136×32 bits register file uses this design to protect against SEU error, the order of magnitude of SEU failure rate is the same with that of using BCH code technique.