A timing failure tolerance design with in-field simultaneous error detection and correction

Abstract

Traditional EDAC (Error Detection and Correction) systems spend several cycles from once timing failure detection to correction, which restricts the error rate around the PoFF (point of first failure) or 1%. This paper presents a new approach to timing failure tolerance design, based on error correction with In-Field Simultaneous detection. A data correction latch is implemented to sample the main register input when timing error is detected, and the correction latch is selected as the output instead of the main register with zero-cycle penalty. So a much higher error rate can be tolerated and the voltage scaling ability of the system can be extended. The proposed In-Filed Simultaneous error detection and correction mechanism is designed and simulation analyzed in a 3-stage commercial processor CK802 at SMIC 40 nm technology, showing 14.5% power saving at fixed throughput and 30.1% performance gain (with 10% error rate) at fixed voltage compared to traditional error correction.