An energy-efficient microprocessor using multilevel error correction for timing error tolerance

Abstract

Traditional error detection and correction (EDAC) techniques are mostly operated near the point of first failure (PoFF) to avoid the unsustainable throughput loss. In this paper we propose a multilevel error correction method according to the timing error characteristics which can be classified into two categories: transient timing error near the PoFF and repeated timing error beyond the PoFF. It enhances the scaling capability of voltage and frequency with low design overhead and can be easily integrated in a traditional flip-flop-based ASIC design flow. The method was implemented in a 3-stage, 32-bit CSKY-CK802 processor under the SMIC 40nm CMOS process and obtained 9.7% optimal throughput improvement and 34% energy efficiency gain with only 1.2% core area overhead compared to global roll-back error correction method.