Multi-valued Logic Gate Research Articles

Electrically and Optically Controllable p–n Junction Memtransistor Based on an Al2O3 Encapsulated 2D Te/ReS2 van der Waals Heterostructure (Small Methods 12/2021)

Inside Front Cover In article number 2101303, Im and co-workers have demonstrated an electrically and optically controllable p-n junction memtransistor using an Al2O3 encapsulated 2D Te/ReS2 van der Waals heterostructure. The hybrid memtransistor shows a high switching ratio at a low operating voltage, high cycling endurance, and long retention time. It successfully functions as a multiterminal non-volatile memory, multivalued logic gate, and synaptic activities by combining electrical and optical inputs.

Area-Selective Chemical Doping on Solution-Processed MoS2 Thin-Film for Multi-Valued Logic Gates.

Multi-valued logic gates are demonstrated on solution-processed molybdenum disulfide (MoS2) thin films. A simple chemical doping process is added to the conventional transistor fabrication procedure to locally increase the work function of MoS2 by decreasing sulfur vacancies. The resulting device exhibits pseudo-heterojunctions comprising as-processed MoS2 and chemically treated MoS2 (c-MoS2). The energy-band misalignment of MoS2 and c-MoS2 results in a sequential activation of the MoS2 and c-MoS2 channel areas under a gate voltage sweep, which generates a stable intermediate state for ternary operation. Current levels and turn-on voltages for each state can be tuned by modulating the device geometries, including the channel thickness and length. The optimized ternary transistors are incorporated to demonstrate various ternary logic gates, including the inverter, NMIN, and NMAX gates.

Constructing a Facile Biocomputing Platform Based on Smart Supramolecular Hydrogel Film Electrodes with Immobilized Enzymes and Gold Nanoclusters.

Herein, fluorescent gold nanoclusters (AuNCs) and horseradish peroxidase (HRP) were simultaneously embedded into self-assembled dipeptide supramolecular films of N-fluorenylmethoxycarbonyl diphenylalanine (Fmoc-FF) on the surface of ITO electrodes (Fmoc-FF/AuNCs/HRP) by using a simple single-step process. In the films, both the fluorescence property of AuNCs and the bioelectrocatalytic property of HRP were well maintained and could be reversibly regulated by pH-sensitive structural changes in the Fmoc-FF hydrogel films. Cu(II)/EDTA in the solution could lead to the aggregation/disaggregation of AuNCs and further quenching/dequenching the fluorescence signal from the films. Meanwhile, the blue complexes formed by Cu(II) and EDTA could produce a UV-vis signal in the solution. In addition, the coordinated Cu(II) in the films enhanced the electrocatalytic capacity toward the reduction of H2O2 and could switch the current signal. A biomolecular logic circuit was built based on the smart film electrode system by using pH, the concentrations of EDTA, Cu(II) and H2O2 as inputs, while the fluorescence intensity (FL), current (I) and UV-vis extinction (E) of the solution as outputs. Various logic devices were fabricated using the uniform platform, consisting of an encoder/decoder, demultiplexer, dual-transfer gate, keypad lock, digital comparator, half adder, and controlled NOT (CNOT) gate. Specifically, an electronic three-value logic gate, gullibility (ANY) gate, was first mimicked in this biocomputing system. This work not only demonstrated the construction of a new type of multivalued logic gate by using a dipeptide micromolecular matrix but also provided a new approach for designing sophisticated biologic functions, establishing smart multianalyte biosensing or fabricating biology information processing through the use of a simple film system.

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented.

Recent Advances on Multivalued Logic Gates: A Materials Perspective.

The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials—ranging from 0D quantum dots to multidimensional heterostructures—are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated.

Population analysis to increase the robustness of molecular computational identification and its extension into the near-infrared for substantial numbers of small objects.

The first population analysis is presented for submillimetric polymer beads which are tagged with five multi-valued logic gates, YES, 2YES + PASS 1, YES + PASS 1, YES + 2PASS 1 and PASS 1 with H+ input, 700 nm near-infrared fluorescence output and 615 nm red excitation light as the power supply. The gates carry an azaBODIPY fluorophore and an aliphatic tertiary amine as the H+ receptor where necessary. Each logic tag has essentially identical emission characteristics except for the H+-induced fluorescence enhancement factors which consistently map onto the theoretical predictions, after allowing for bead-to-bead statistical variability for the first time. These enhancement factors are signatures which identify a given bead type within a mixed population when examined with a 'wash and watch' protocol under a fluorescence microscope. This delineates the scope of molecular computational identification (MCID) for encoding objects which are too small for radiofrequency identification (RFID) tagging.

Room-Temperature Quantum Ballistic Transport in Monolithic Ultrascaled Al-Ge-Al Nanowire Heterostructures.

Conductance quantization at room temperature is a key requirement for the utilizing of ballistic transport for, e.g., high-performance, low-power dissipating transistors operating at the upper limit of “on”-state conductance or multivalued logic gates. So far, studying conductance quantization has been restricted to high-mobility materials at ultralow temperatures and requires sophisticated nanostructure formation techniques and precise lithography for contact formation. Utilizing a thermally induced exchange reaction between single-crystalline Ge nanowires and Al pads, we achieved monolithic Al–Ge–Al NW heterostructures with ultrasmall Ge segments contacted by self-aligned quasi one-dimensional crystalline Al leads. By integration in electrostatically modulated back-gated field-effect transistors, we demonstrate the first experimental observation of room temperature quantum ballistic transport in Ge, favorable for integration in complementary metal–oxide–semiconductor platform technology.

Simple, fast, label-free, and nanoquencher-free system for operating multivalued DNA logic gates using polythymine templated CuNPs as signal reporters

Boolean logic devices play a key role in both traditional and nontraditional molecular logic circuits. This kind of binary logic, in which each bit is coded by (0, 1), has only two output states—on or off (or high/low). Because of the finite computing capacity and variation, it is facing challenges from multivalued logic gates while processing high-density or uncertain/imprecise information. However, a low-cost, simple, and universal system that can perform different multivalued logic computations has not yet been developed, and remains a concept for further study. Herein, taking the ternary OR and INHIBIT logic gates as model devices, we present the fabrication of a novel simple, fast, label-free, and nanoquencher-free system for multivalued DNA logic gates using poly-thymine (T) templated copper nanoparticles (CuNPs) as signal reporters. The mixture of Cu2+ and ascorbic acid (AA) is taken as a universal platform for all ternary logic gates. Different kinds of poly-T strands and delicately designed complementary poly-adenine (A) strands are alternatively applied as ternary inputs to exhibit the ternary output states (low/0, medium/1, high/2). Notably, there are no nanoquenchers in this platform as poly-A strands can function as not only inputs but also efficient inhibitors of poly-T templated CuNPs. Moreover, all DNA are unlabeled single-strand DNA that do not need sophisticated labeling procedures or sequence design. The above design greatly reduces the operating time, costs, and complexity. More importantly, the ternary logic computations can be completed within 20 min because of the fast formation of CuNPs, and all of them share the same threshold values.

Multifunctional Graphene/DNA-Based Platform for the Construction of Enzyme-Free Ternary Logic Gates.

In this work, we have successfully realized multivalued logic circuits including ternary INHIBIT and ternary OR logic gates in an enzyme-free condition by integration of graphene oxide and DNA for the first time. Compared to the binary logic gate with two states of "0" and "1", the multivalued logic gate contains three different states of "0", "1", and "2", which can increase the information content in a system and further improve the ability of information processing. Such types of multivalued logic operations provide a wider field of vision toward DNA-based algebra logical operations to make applications more accurate with complexity reduction and accelerate the development of advanced logic gates.

A New Biocomputing Platform Based on Potential- and pH-Sensitive Bioelectrocatalysis and Layer-by-Layer Films Assembled with Graphene Derivatives and Weak Polyelectrolyte

In the present work, (PAH/GO)n layer-by-layer (LbL) films have been assembled on the surface of electrodes based on the electrostatic interaction between graphene oxide (GO) and polyallylamine (PAH). At the LbL film electrodes, the electroactive probe K3Fe(CN)6 in buffers demonstrates potential-sensitive cyclic voltammetric (CV) behavior because of the transition between GO and its reduced form (rGO) in the films at different potentials. K3Fe(CN)6 in buffers also shows pH-responsive CV behavior in the LbL films, due to the electrostatic interactions between the films and the probe at different pH. The multiple-stimuli CV properties of the system are used as the potential- and pH-responsive ON-OFF switches and further utilized to perform the electro-reduction of H2O2 catalyzed by horseradish peroxidase (HRP) and mediated by the probe in solution. With the same platform, a connected logic gate network with 3 inputs and 4 outputs, a decimal parity checker, and a ternary INHIBIT logic gate, are fabricated. This work provides the first example of how to construct a multi-valued logic gate system on the foundation of graphene derivatives and enzymatic catalytic reactions. It opens a new possibility to mimic multi-functioned logic networks by using bioelectrocatalytic platform.

Analytical Distinction Between Cntfet Based And Mosfet Based Srams And Logic Gates

In this review, we compare the distinct properties of Carbon Nanotube Field Effect Transistor (CNTFET) based applications with MOSFET based applications in memory and digital electronics technology. In nanoelectronics circuitry, CNTFET has opened new dimensions with extreme opportunities of improvement in circuit performance due to its extreme mobility, ballistic conduction and so forth. Apart from being an excellent conductor, CNTFET can also be used as a memory unit for its good stability in storing a data bit and as digital circuits (multi-valued logic gates) for its better PDP and sensitivity. This paper discusses the design and read-write mechanisms of 6T and 8T CNTFET SRAM cell and a comparative study among themselves based on their corresponding advantages and disadvantages. Moreover, superiority of CNTFET SRAM over MOSFET SRAM is analyzed in terms of certain phenomena (such as scattering, defecttolerance and ability to work in low power supply) observed in them. At last, different types of ternary logic gates and how they will persevere the limitations of MOSFET logic gates with its PDP value, less power dissipation and better longevity have been discussed.

Multi-Valued Logic Gates based on Ballistic Transport in Quantum Point Contacts

Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

Design of polarization encoded all-optical 4-valued MAX logic gate and its applications

Quaternary maximum (QMAX) gate is one type of multi-valued logic gate. An all-optical scheme of polarization encoded quaternary (4-valued) MAX logic gate with the help of Terahertz Optical Asymmetric Demultiplexer (TOAD) based fiber interferometric switch is proposed and described. For the quaternary information processing in optics, the quaternary number (0, 1, 2, 3) can be represented by four discrete polarized states of light. Numerical simulation result confirming the described methods is given in this paper. Some applications of MAX gate in logical operation and memory device are also given.

Information Processing Schemes Based on Monolayer Protected Metallic Nanoclusters

Nanostructures are potentially useful as building blocks to complement future electronics because of their high versatility and packing densities. The fabrication and characterization of particular nanostructures and the use of new theoretical tools to describe their properties are receiving much attention. However, the integration of these individual systems into general schemes that could perform simple tasks is also necessary because modern electronics operation relies on the concerted action of many basic units. We review here new conceptual schemes that can allow information processing with ligand or monolayer protected metallic nanoclusters (MPCs) on the basis of the experimentally demonstrated and theoretically described electrical characteristics of these nanostructures. In particular, we make use of the tunnelling current through a metallic nanocluster attached to the electrodes by ligands. The nanostructure is described as a single electron transistor (SET) that can be gated by an external potential. This fact permits exploiting information processing schemes in approximately defined arrays of MPCs. These schemes include: (i) binary, multivalued, and reversible logic gates; (ii) an associative memory and a synchronization circuit; and (iii) two signal processing nanodevices based on parallel arrays of MPCs and nanoswitches. In each case, the practical operation of the nanodevice is based on the SET properties of MPCs reported experimentally. We examine also some of the practical problems that should be addressed in future experimental realizations: the stochastic nature of the electron tunnelling, the relatively low operation temperatures, and the limited reliability caused by the weak signals involved and the nanostructure variability. The perspectives to solve these problems are based on the potentially high degree of scalability of the nanostructures.

Logical progression

Single-electron transistors have been made to function as multi-valued logic gates

Single-electron-based flexible multivalued logic gates

Single-electron transistor (SET)-based multivalued (MV) not-AND (NAND) and not-OR (NOR) logic cells were implemented on a silicon-on-insulator chip. Depending on the ways of connecting two SETs with a field-effect transistor, the voltage transfer characteristics show typical NAND or NOR gate functions for various input voltages, which are binary, MV, and binary-MV mixed. Moreover, the switching functionality of our NAND (NOR) can convert to OR (AND) operation by simply adjusting their initial input voltages. These flexible two-input logic gates are expected to provide four basic arithmetic cells for the SET MV logic gate family.

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.

Multivalued logic gates for quantum computation

We develop a multi-valued logic for quantum computing for use in multi-level quantum systems, and discuss the practical advantages of this approach for scaling up a quantum computer. Generalizing the methods of binary quantum logic, we establish that arbitrary unitary operations on any number of d-level systems (d > 2) can be decomposed into logic gates that operate on only two systems at a time. We show that such multi-valued logic gates are experimentally feasible in the context of the linear ion trap scheme for quantum computing. By using d levels in each ion in this scheme, we reduce the number of ions needed for a computation by a factor of log d.