Multistage Interconnection Networks Research Articles

D-Dimensional (d ≥ 3) shuffle interconnections

The need for d-dimensional (d >/= 3) interconnection patterns occurs if d-dimensional data cubes have to be interconnected. The formal definition of such patterns, presented here, is based on the mixed radix numbering of the d-tuple data points. Because each coordinate of a d-dimensional data cube may be factorized in a different way, a family of interconnection patterns is obtained that increases with respect to the dimension of the data cubes. The properties of d-dimensional patterns are analyzed, and their realization in the frequency domain is described. Methods for the three-dimensional layout of the patterns are presented. The application of d-dimensional patterns within multistage interconnection networks is discussed.

Transformation of three-dimensional shuffle patterns

Formulas are presented for the transformation of three-dimensional shuffle patterns into the twodimensional domain. The results are applied to the transformation of the interstage patterns of three-dimensional multistage interconnection networks into their isomorphic two-dimensional patterns (and vice versa). This paper explains material in J. Giglmayr, "Classification scheme for 3-D shuffle interconnection patterns," Appl. Opt. 28, 3120-3128 (1989) and corrects some algebraic results.

Hardware support for high-priority traffic in VLSI communication switches

Interconnection networks used in large multiprocessors and multicomputers are composed of small n × n switches. The architecture of these switches is critical for achieving high-bandwidth low-latency interprocessor communication. Low-latency communication is particularly important for interprocessor traffic generated for devices that operate under real-time constraints, as well as certain other system activities, such as exception handling. In order to meet this requirement, it may be necessary to provide special support for such high-priority traffic in many multiprocessor and multicomputer systems. We discuss the design of n × n switches that can be used to construct communication networks that provide low-latency communication for high-priority traffic. We focus on the design of the internal buffers, specifically on buffers where storage is statically or dynamically partitioned between normal traffic and high-priority traffic and where packets can be handled in non-FIFO order. We evaluate alternative designs and configurations in the context of a multistage interconnection network. Our simulations show that a slightly modified version of the recently introduced dynamically allocated multi-queue buffer can provide superior support for high-priority traffic, at a relatively low cost.

Design trade-offs in optoelectronic parallel processing systems using smart-SLMs

Optoelectronic devices with free-space optical interconnections offer new possibilities in massively parallel processing. The trade-offs involved in system design and device selection for optoelectronic implementations are examined. System design trade-offs are approached from algorithmic and technological standpoints. From the algorithmic standpoint, new architectures based on expander graphs, that have been shown to provide low-contention fault-tolerant communication, are discussed. Optoelectronic systems which implement such random graphs can be folded to reduce the hardware cost or unfolded to increase bandwidth. They can also be partially folded by increasing the grain size or by reducing the randomness of the graph topology to reduce the complexity of the interconnection holograms. An optoelectronic and a VLSI implementation of a multistage interconnection network are compared from a technological standpoint. Physical design parameters, such as the chip size or the number of phase levels of the interconnection holograms, are related to the system design metrics such as bandwidth, volume, area and power. It is shown that the optoelectronic implementations have higher performance and are more cost-effective than VLSI implementations. These results are also used to provide general guidelines for device selection in the design of smart pixels/smart spatial light modulators based optoelectronic systems.

The ATM shuffleout switching fabric: Design and implementation issues

AbstractThis paper describes the design and implementation aspects of the Shuffleout switch, a new class of switching fabric architectures. The key points of this structure are the adoption of a memoryless multistage interconnection network and a new packet routing strategy. Compared to the basic multistage shuffle interconnection network of Shuffleout, adopting 2×4 switching elements, three other architectures of the interconnection network are described, which use larger switching elements, that is 4×6, 3×5 and 4×8. Adopting these upgraded structures aims not only at decreasing the number of interconnection network stages that provide a given cell loss probability, thus reducing the switching fabric complexity, but also at improving fairness in the network. The VLSI hardware design of a switching element and of a chip is then described with reference to the basic Shuffleout structure, with design and implementation details on their major functional blocks. Finally a complexity comparison of the different enhanced architectures is assessed.

Reliability of a class of multistage interconnection networks

The reliability of extra-stage interconnection networks is discussed. Three types of reliability are analyzed: terminal reliability, which is the probability that at least one fault-free path exists between a given input-output pair: network reliability, which is the probability that at least one fault-free path exists between every input-output pair; and broadcast reliability, which is the probability that at least one fault-free path exists between a given input and all outputs. A recursive expression for the broadcast reliability is obtained. Tight bounds are derived for the network reliability. The numerical results indicate that for practical networks (i.e. when network reliability is at least 0.5) the difference between the upper bound and the lower bound is no more than 2% of the lower bound.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-routing algorithms for strongly regular multistage interconnection networks

This paper presents a self-routing algorithm for a class of permutations that can be represented as linear transportations and complementations. This class includes bit-permute-complement (BPC) [6] and several of other frequently used permutations. The same problem for a Benes̃ or a shuffle-exchange network was considered earlier by Boppana and Raghavendra. This paper considers a more general problem by considering a broader class of multistage interconnection networks that includes these networks along with variety of others. For this class of interconnection networks, Nassimi presented a routing algorithm for BPC class. In effect, this paper considers the problem of routing a larger class of permutations than that considered by Nassimi for a broader class of networks than that considered by Boppana and Raghavendra.

Design and analysis of a generalized architecture for reconfigurable m-ary tree structures

A generalized architecture is presented for reconfigurable m-ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture with m/sup k/ processing elements or nodes (where k is any integer >1) is implemented with a k-stage MIN. A single control code issued to the MIN establishes a distinct m-ary tree configuration among the nodes. The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The reconfigurability of the architecture is proved, and the results of the analysis are utilized to provide a procedure to synthesize the m-ary tree configuration that is generated for any given control code. Considerations for implementing the switching elements of the MIN are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance evaluation of circuit switched multistage interconnection networks using a hold strategy

The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n/sup 2/+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained. >

UPP graphs and UMFA networks-architecture for parallel systems

A graph with unique path property (UPP) has 2/sup n/ vertices and a unique path of length n between every two vertices. These graphs are very important in the design of architectures and algorithms for interconnection networks. Given two UPP graphs, an algorithm is introduced to determine isomorphism between the graphs. A construction is given for nonisomorphic UPP graphs and a lower bound of 2/sup x/, where x=(2/sup n+1/-3-2)/9, nonisomorphic graphs with 2/sup n/ vertices is shown. UMFA (uniform minimal full access) networks are multistage interconnection networks that use the same interconnection pattern between every two consecutive stages. These networks are derived from UPP graphs, and the most known network of this type is the Omega network. The problem of rearrangeability of UMFA networks is discussed. >

Performance analysis of multistage interconnection network configurations and operations

A performance evaluation using both analytical and simulation models, of circuit-switching multistage interconnection networks in aspects of configurations and operations is presented. Two configurations of the networks, single and dual, are evaluated. Network operations considered include conflict resolution strategies and communication strategies. Two different conflict resolution strategies, drop and hold, are analyzed. New analyses using Markov chains, are given, and are verified by simulation results. In the single-network configuration, it is shown that the drop strategy is better than the hold strategy for randomly distributed traffic. In the dual network configuration, five different communication strategies are investigated, and the optimum performance level is shown to be dependent on the length of the data transfer time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Topology of efficiently controllable Banyan multistage networks

Due to their unique path property, Banyan multistage interconnection networks (MINs) can be self-routed using control tags. This paper introduces a number of routing control classes of MINs and studies their structure. These include the D-controllable networks where the control tags are the destination labels, the FD-controllable networks where the control tags are functions of the destination labels, and the doubly D- or FD-controllable networks which are D- or FD-controllable forward and backward. The paper shows that all D- and FD-controllable networks have a recursive structure, and that all doubly D-controllable (resp., FD-controllable) networks are strictly (resp., widely) functionally equivalent to the baseline network. The subclass of MINs where the interconnections are operations on bits or digits is also studied and shown to be doubly FD-controllable and hence equivalent to the baseline. Finally, the paper presents an efficient, parallel algorithm that relabels the terminals of the baseline to simulate any network in that subclass.

Detection and location of multiple faults in baseline interconnection networks

An algorithm for fault diagnosis (detection and location) of baseline interconnection networks in the presence of multiple faults is presented. This algorithm requires 2(1+log/sub 2/ N) tests, where log/sub 2/ N is the number of stages. Multiple fault diagnosis is possible provided: (a) there exists no logically erroneous and unidentified outputs in each faulty switching element and (b) multiple link faults (of the type stuck-at-0 stuck-at-1) do not exist in the network. Fault location is accomplished using an iterative process which checks each stage of the multistage interconnection network. A new functional description of the network is introduced to facilitate fault location.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A cost-effective combining structure for large-scale shared-memory multiprocessors

A cost-effective combining structure to alleviate hot-spot contention is proposed. The key idea is that the combining function is separated from the routing function, so that a binary tree-based combining configuration becomes feasible. The combining element for realizing the new structure has only one wait buffer and one combining logic, involving less hardware than the element used in earlier combining networks. More importantly, the number of constituent combining elements in such a structure with size N is reduced to O(1/log/sub 2/ N) of that required in the previous design. The proposed combining structure in conjunction with a regular multistage interconnection network can remove hot-spot contention effectively in any sized system at a considerably lower cost, and appears readily suitable for use in some applications. >

ROUTING IN RANDOM MULTISTAGE INTERCONNECTIONS NETWORKS: COMPARING EXHAUSTIVE SEARCH, GREEDY AND NEURAL NETWORK APPROACHES

The problem of establishing point-to-point communication routes in a random multistage interconnection network (RMIN) is addressed. A neural network routing scheme is presented. This routing scheme is compared to two more traditional routing techniques—namely, exhaustive search routing and greedy routing. The main criterion that is examined is the ability of each routing methodology to solve routing problems. Results are obtained through simulation of the routing methodologies for three different RMINs. The sample RMINs are relatively small since the neural network router in its present form will only be competitive for small RMINs. The simulations show that the three routing schemes perform similarly for the three sample RMINs. Other criteria that will be touched upon are the speed and the resource utilization of each routing methodology and the pros and cons of each approach will be discussed. The results suggest that neural network routers may be appropriate for some communication applications involving RMINs.

A closed form formula for the normalized throughput of unbuffered multistage interconnection networks

Abstract The normalized throughput of an unbuffered multistage interconnection network (MIN) under the uniform traffic model can be computed iteratively [6] or recursively [7]. However, the asymptotic performance of such networks as the number of stages increases cannot be determined using these procedures. A closed form formula for the normalized throughput of unbuffered MINs is presented in this paper. The new formula is proved by mathematical induction on the number of stages. The major advantage of the closed form formula is that the asymptotic performance of unbuffered square MINs can be easily determined. The formula is generalized to unbuffered MINs in the presence of nonidentical input rates and non‐square switch size.

Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard-wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self-routeing multistage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non-blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues.

Analytic models for multistage interconnection networks

Central to all parallel architectures is a switching network which facilitates the communication between a machine's components necessary to support their cooperation. Multistage interconnection networks (MINs) are classified and analytic models are described for both packet-switched and circuit-switched MINs with asynchronous transmission mode. Under strong enough assumptions, packet switching can be modeled by standard queuing methods, hence providing a standard against which to assess approximate models. We describe one such approximate model with much weaker assumptions which is more widely applicable and can be implemented more efficiently. To model circuit switching requires a different approach because of the presence of passive resources, namely multiple links through the MIN which must be held before a message can be transmitted and throughout its transmission. An approximate analysis based upon the recursive structure of a particular MIN topology which yields accurate predictions when compared with simulation is described.

Two cost‐effective fault‐tolerant multistage interconnection networks

Abstract This paper introduces two concepts for building fault‐tolerant multistage interconnection networks (MIN). The first one is to add multiplexers/demultiplexers at the front/back end of a pre‐constructed network which may be a uniquepath MIN or a fault‐tolerant one. The second one is to integrate multiple fault‐tolerant MINs to form a larger and even more reliable one. Based upon the first concept, we propose a new fault‐tolerant MIN, the Path Sharing Network, which is derived by adding multiplexers/demultiplexers at the front/back end of the Banyan MIN. The Recursive Path Sharing Network is also proposed by integrating two fault‐tolerant MINs based upon the second concept. The reliability and cost‐effectiveness of the proposed networks are analyzed and compared with other fault‐tolerant MINs. Surprisingly, the proposed networks are better than EGN‐4 which was shown to be better than ESC, 3‐Rep and INDRA.

MVAMIN: Mean value analysis algorithms for multistage interconnection networks

A new approach to the modeling of multistage interconnection networks (MIN) based on queueing theory is presented in this paper. The network operates in an asynchronous, decentralized packet-switched mode and has buffers at each queueing center. The analytical approach involves basically three steps, namely, the building of a closed multiclass queueing model for the MIN system, the derivation of input parameters for the model, and finally solving the model using a heuristic mean value analysis algorithm. Networks operating in both tightly coupled and loosely coupled environments are analyzed. Separate networks are assumed for packets from processors to memories and from memories to processors in the case of a tightly coupled system. We derive a set of routing equations corresponding to the probabilities of memory requests through which systems with arbitrary memory reference patterns can be analyzed. Here, N is the number of processors or memories with n = log 2 N number of stages. An approximate technique of aggregation is also developed to significantly reduce the computational complexity of the above analysis while maintaining the accuracy of the model. The accuracy of our models has been verified by comparing the analytical results with those obtained from simulation. The simulations are based on 95% confidence level with a relative confidence interval width of 0.005.