Hardware support for high-priority traffic in VLSI communication switches

Abstract

Interconnection networks used in large multiprocessors and multicomputers are composed of small n × n switches. The architecture of these switches is critical for achieving high-bandwidth low-latency interprocessor communication. Low-latency communication is particularly important for interprocessor traffic generated for devices that operate under real-time constraints, as well as certain other system activities, such as exception handling. In order to meet this requirement, it may be necessary to provide special support for such high-priority traffic in many multiprocessor and multicomputer systems. We discuss the design of n × n switches that can be used to construct communication networks that provide low-latency communication for high-priority traffic. We focus on the design of the internal buffers, specifically on buffers where storage is statically or dynamically partitioned between normal traffic and high-priority traffic and where packets can be handled in non-FIFO order. We evaluate alternative designs and configurations in the context of a multistage interconnection network. Our simulations show that a slightly modified version of the recently introduced dynamically allocated multi-queue buffer can provide superior support for high-priority traffic, at a relatively low cost.