Multistage Interconnection Networks Research Articles

An analysis of the hot spot contention and message combining on the simple serial synchronized‐multistage interconnection network

AbstractSimple serial synchronized (SSS) multistage interconnection network (MIN) is a processor‐memory connection network that has a high performance/cost ratio, where the packet is inputted and switch synchronously in the MIN, which has a high pass‐through ratio and is composed of simple elements. This paper evaluates the effect of the hot spot contention and the effect of the synchronous bit‐serial (SBS) message combining in SSS‐MIN, by the theoretical analysis based on probability and simulation. In contrast to conventional MIN, there does not arise a complete tree saturation in SSS‐MIN, but an area, to which the access is difficult, is produced according to the relative position to the hot spot contention. From such a viewpoint, an analysis method for the pass‐through ratio is presented, which considers the position of the switching element to the hot spot. It is verified as a result of evaluation that the proposed method of analysis gives a result close to that of simulation, so long as the access to the hot spot and the connection network architecture stay within a practical range. It is also seen that the pass‐through ratio is deteriorated less in SSS‐MIN by the hot spot contention than in the conventional MIN, and the effect can be almost completely eliminated by the SBS message combining. When a multiprocessor system is actually constructed, performance deterioration due to hot spot contention is greater than in the case where only the pass‐through ratio is considered. This can also be eliminated almost completely by the SBS message combining.

KSMINs: knockout switch-based multistage interconnection networks for high-speed packet switching

We propose knockout switch-based multistage interconnection networks (KSMINs) for fast packet switching, combining the well-known knockout switch and the concept of multistage interconnection networks. The main objective is to reduce the severe pin requirements of large knockout switches through a phased address filtering. We present an approximate Markov-chain model of KSMINs to study the performance of KSMINs with different numbers of address-filtering phases. The model is shown to be accurate within 5% for all the cases considered and within 20% for the meaningful cases of the buffer sizes /spl ges/4. For the (256/spl times/256) KSMIN, two-phase address filtering based on the (16/spl times/16) knockout switches is shown to perform very closely to the single-stage knockout switch for a reduced hardware cost.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Distributed fault diagnosis in multistage network-based multiprocessors

This paper is concerned with a distributed, system level fault diagnosis scheme for multistage network-based multiprocessors. The target system, which we choose as a representative, employs a multistage interconnection network with 4/spl times/4 switching elements. We propose a fast diagnostic method which uses a quadtree and its coupler structure. These two quadtree structures partition the system into a number of link-independent groups. This partitioning provides an important diagnostic property; the communication paths in each link-independent group are either identical or disjoint. Several previous works in fault diagnosis investigated the multistage interconnection network only. This paper presents an entire multiprocessor diagnosis, including the detection and location of single faults caused by processor nodes, switching elements, and communication links. In addition, the diagnosis of a group of multiple faults partitioned by the tree structures is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparative performance evaluation of hot spot contention between MIN-based and ring-based shared-memory architectures

Hot spot contention on a network-based shared-memory architecture occurs when a large number of processors try to access a globally shared variable across the network. While multistage interconnection network (MIN) and hierarchical ring (HR) structures are two important bases on which to build large scale shared-memory multiprocessors, the different interconnection networks and cache/memory systems of the two architectures respond very differently to network bottleneck situations. In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Both nonblocking MIN-based and HR-based architectures are classified, and analytical models are described for understanding network differences and for evaluating hot spot performance on both architectures. The analytical comparisons indicate that HR-based architectures have the potential to handle various contentions caused by hot spots more efficiently than MIN-based architectures. Intensive performance measurements on hot spots have been conducted on the BBN TC2000 (MIN-based) and the KSR1 (HR-based) machines. Performance experiments were also conducted on the practical experience of hot spots with respect to synchronization lock algorithms. The experimental results are consistent with the analytical models, and present practical observations and an evaluation of hot spots on the two types of architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New bounds on the reliability of augmented shuffle-exchange networks

The reliability resulting from two forms of redundancy, spatial and temporal, in multistage interconnection networks is examined. The extra-stage shuffle-exchange network (SEN+) which is an example of the former is investigated here. The SEN+ is decomposed into two subnetworks connected by two extreme stages. Given k random faults in one subnetwork, our problem reduces to estimating the maximum and minimum number of switches in the other subnetwork that must be operational for full access, i.e., connection between every input (processor) and output (memory) pair. This investigation results in obtaining analytical estimates for the upper and lower bounds on its reliability which are a substantial improvement over existing ones. We next examine the effect of wrap-around connections from each output node to its corresponding input node. This may provide a path between a source-destination pair under faults by diverting a given packet through one or more intermediate destinations. The reliability offered by this scheme that provides temporal redundancy is also estimated and compared with the scheme employing hardware redundancy. >

Multicommodity flows in simple multistage networks

AbstractIn this paper, we consider the integral multicommodity flow problem on directed graphs underlying two classes of multistage interconnection networks. In one direction, we consider three‐stage networks. Using existing results on (g, f)‐factors of bipartite graphs, we show sufficient and necessary conditions for the existence of a solution when the network has at most two secondary switches. In contrast, the problem is shown to be NP‐complete if the network has three or more secondaries. In a second direction, we introduce a recursive class of networks that includes multistage hypercubic networks (such as the omega network, the indirect binary n‐cube, and the generalized cube network) as a proper subset. Networks in the new class may have an arbitrary number of stages. Moreover, each stage may contain identical switches of any arbitrary size. The notion of extrastage networks is extended to the new class, and the problem is shown to have polynomial time solutions on r‐stage networks where r = 3 or where each link has a unit capacity and r ≥ 3. The latter result implies an efficient algorithm for deciding admissible permutations on conventional extrastage hypercubic networks. In contrast, we show that the multicommodity flow problem is NP‐complete on extrastage networks, even if r = 6, each link has an integral capacity ≤ 3, and all flow demands are equal.

Architecture of a parallel machine: Cenju‐3

AbstractCenju‐3 is a parallel computer in which up to 256 processing elements (PEs) are connected by a highspeed multistage interconnection network. In designing the system, the architecture is tuned for up to a 256 processor system. A VR4400 with 1 MB of secondary cache memory is implemented on a multi‐chip‐module to realize a compact and high‐performance PE. The multistage network is implemented very compactly. The number of the cables is equal to the number of processors. The dedicated network interface hardware designed for the system achieves low latency and high throughput. This paper presents the machine architecture and its evaluation.

Routing and performance of the double tree (DOT) network

The paper deals with the analysis of an irregular multistage interconnection network called the double tree (DOT) network. A dynamic shortest path routing algorithm for the packet switching DOT network is proposed. The DOT network, being an irregular network, can provide biased pairwise service to favoured connections. Its performance under varying degrees of localised communication is analysed. A comparison with the Omega network is also made.

The composite banyan network

A new multipath multistage interconnection network called the composite banyan network is proposed. The network incorporates both the banyan and the reverse banyan networks and is constructed by superimposing the two. The basic building blocks in the composite banyan network are 3/spl times/3 switching elements with log/sub 2/N stages. A major advantage of the composite banyan network over existing networks with 3/spl times/3 SEs is an efficient and fast control algorithm that sets up a path between any source and destination pair. Instead of complex numerical calculations, the network can easily generate a primary routing tag and alternate tags through simple binary operations. Also, the network has a lot of favorable features, including regularity, symmetry, and easy rerouting capability under faults and conflicts. It is shown that at least two totally disjoint paths exist between any source and destination pair, which increase the degree of fault-tolerance. A deterministic permutation routing algorithm is also developed for the 8/spl times/8 composite banyan network, Using a simple tabular method, it is shown that the algorithm always finds a set of conflict-free tags.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An extensible fault-tolerant network architecture

All-to-all personalized exchange (ATAPE) is an inspired process to speedup the parallel and distributed computing. Recently, ATAPE algorithms were successfully applied on multistage interconnection networks (MINs), including baseline and butterfly networks. However, routing of those algorithms on MINs relies on switch-patterns for stage-control from sources (S), which is a half-routing solution since they cannot perform a full self-routing with the (S, D) protocol for all MINs. In this paper, first we propose a full-routing solution of the realizing ATAPE on a class of d-nary-switch MINs+ (i.e., baseline+, butterfly+, etc.). Our ATAPE can be embedded on-chip effectively for not only (S, D) self-routing but also stage-/switch-control routing. Two embedded ATAPE functions incorporate with multi-stage pipelining are proposed in optimal O(N+log2N): 1. a (default) static function D=S XOR (C+order) mod N and 2. an (optional) f-in-1 dynamic function D=ρ [(S+C+order) mod N] with the incrementing counter C=0 to N−1. Second, we introduce a crossbar of MINs+ with fewer delay-stages to achieve the ultimate ATAPE embedding. Finally, experimental results of applying ATAPE on such MINs+ are confirmed fruitfully, including the ATAPE-based NxN-matrix transposition in O(N+log2N), which yields the significant speedup.

THE RING-BANYAN NETWORK: A FAULT TOLERANT MULTISTAGE INTERCONNECTION NETWORK FOR MULTIPROCESSOR SYSTEMS

In this paper, we propose a new fault tolerant multistage interconnection network (MIN) and a new adaptive self-routing scheme for the network. It can provide more multiple paths than the related previous networks between an input/output pair of a network by adding extra links between switching elements in the same stage and modifying the self-routing scheme of the banyan network. Our routing scheme is as simple as that of the banyan network, which is based on the topological relationships among the switching elements (SE’s) that render a packet to the same destination with the regular self-routing, which are discovered in this paper. We present an algebraic proof to show the correctness of this scheme, and an analytic reliability analysis to provide quantitative comparisons with other networks, which shows that the new network is more cost effective than the banyan network and other augmented MIN’s in terms of the reliability.

Performance Study of Packet Switching Multistage Interconnection Networks

This paper provides a performance study of multistage interconnection networks in packet switching environment. In comparison to earlier work, the model is more extensive ‐ it includes several parameters such as multiple-packet messages, variable buffer size ,a ndwait delay at a source. The model is also uniformly applied to several representative networks and thus provides a basis for fair comparison as well as selection of optimal values for parameters. The complexity of the model required use of simulation. However, a partial analytical model is provided to measure the congestion in a network.

Fault-Tolerant Routing in MIN-Based Supercomputers

We study methods for routing data in supercomputers that use multistage interconnection networks (MINs), in the presence of faulty components in the network. These methods are applicable to multiprocessors such as IBM GF11 and RP3. These methods are based on the concept of dynamic full access (DFA), which refers to the ability of the network to route data from any processor in the system to any other processor in a finite number of passes through the network. We introduce a graph model called the DFA graph of a MIN and show how it can be used to determine the DFA capability of the MIN under a given set of network faults. When the faults in the network satisfy certain special properties, we present algorithms for routing • any arbitrary permutation in a faulty Benes network, and • any Omega permutation in a faulty Omega network. These algorithms are simple and operate in a distributed fashion. These techniques allow a supercomputer to efficiently realize permutations of data needed in a parallel computing environment despite the presence of faults in the network.

Modeling of optical devices for the design of multistage interconnection network systems

Guidelines of the modeling of an all-optical architecture is presented. This basic architecture is universal and flexible. It can be used as the switching building block for a number of interconnection networks. The power analysis of an all optical buffering architecture [1] that can be interfaced with such an element is discussed. The modeling analysis is given in terms of the switch model, the multistage model and the power analysis of the optical buffer. The architecture uses bistable optical devices such as Fabry-Perot etalons, SEED and S-SEED. A number of important issues remain to be addressed, such as the use of different nonlinear optical devices, synchronization, and simulation.

Multicasting in Generalized Multistage Interconnection Networks

Multistage interconnection networks (MIN) are popular in switching and communication applications. It is also well known as a hypercube derived architecture, offering a fixed-degree alternative to hypercube for a large class of applications. Message routing strategy in MIN is well known, however, multicasting issues for MIN has not been considered. This paper formulates the multicasting problem for MIN. We demonstrate that reordering the dimensions in MIN can lead to traffic reduced multicasting. This leads to the formulation of optimality criteria in MIN multicast operation. Traffic optimum multicasting in MIN is shown as a NP-Complete problem. We present a polynomial time greedy heuristic to generate traffic reduced multicast in MIN. The greedy approach generates a locally optimum solution. Analytical study and simulation results are presented showing the traffic reduction that can be obtained using our approach over traditional linearly ordered dimensions approach.

On a fault-tolerant multistage interconnection network

This paper introduces a class of fault-tolerant multistage interconnection networks (MINs) named as Augmented Baseline Networks (ABNs). A technique is described for making MINs more reliable and cost-effective. The proposed technique results in a reduced number of stages in a network. Performance and reliability studies show that ABNs achieve a significant improvement over unique-path MINs and compare favorably with other multiple path MINs.

Performance analysis of augmented partitioned multistage interconnection networks

In previous work, a novel scheme for constructing fault-tolerant multistage interconnection networks (MINs) was presented. The constructed augmented partitioned MINs (APMINs) were evaluated using a switch level fault model in terms of full access (FA) and dynamic full access (DFA) measures. The simulation results showed that the proposed scheme significantly improved the fault-tolerant capability of MINs. Based on the small synchronous clock scheme, we first analyze the performance of this class of synchronous packet-switched APMINs. We then evaluate the performance of the APMIN-based tightly coupled and loosely coupled multiprocessor systems using a hybrid probabilistic and queueing model. The performance of this class of fault-tolerant multiprocessor systems and that of systems employing Omega and modified Omega (MD-Omega) networks are also compared.

Architectural framework for optical frequency division multiplexing systems based on regular space-frequency interconnections

The paper describes a multistage interconnection network (MIN) with regular interconnections in three dimensions (two space dimensions and the third dimension is the frequency) and dimension-dependent switches. (Regular interconnections mean that the same interconnection principles are applied throughout the stages of the MIN.) The frequency domain is organized by introducing artificial dimensions. The architecture is interpreted as an optical frequency division multiplexing (OFDM) system with multidimensional interconnections and switches where the dimension is an additional design parameter. The multidimensional interconnections may be implemented using a combination of space and frequency channels. The frequency interconnections (data movements between channels) are expressed by the Kronecker product (KP) of permutation matrices. In this case the number of frequency conversion (FC) operations and the number of frequency channels crossed during the generation of interconnections and switching decreases. The architectural principles presented are of general interest for the study of transmission and processing in arbitrary large scale interconnection systems implemented in the 3-D physical space. >

Reflective interconnection networks

In this paper, a class of single-sided multiprocessor multistage interconnection networks (MINs), which we call ‘reflective’ networks, is proposed. A common characteristic of reflective networks is that as requests pass through the network, at some point they are reflected back to the same side rather than passed to the opposite side as in double-sided multistage interconnection networks. This leads to a logarithmic delay between processors and memory which is often much less than in double-sided MINs, many routes through the networks which provides for increased performance and significant fault tolerance, and good physical properties for scalability. Here, reflective networks are analyzed and various routes through the network characterized. Their performance is compared to existing networks using simulation under circuit-switched and packet-switched modes of operation. Both fault-free performance and performance in the presence of faults are presented. We prove that there are a very large number of routes available in general, and often many short routes. There are disjoint routes which can be used very effectively to avoid faulty parts of the network.

Fault Reconfiguration for the Near Neighbor Task in a Multistage-Network MIMD System

Dynamic fault reconfiguration in an MIMD environment with a multistage interconnection network is considered. The near neighbor class of problems, which involve fundamental parallel processing algorithms such as partial differential equations and low level image processing algorithms, are chosen as the target application in such an environment. It is shown that dynamic fault reconfiguration can be achieved efficiently without any additional or modified hardware in case of (permanently) faulty processors. Two types of multistage networks are considered: general multistage networks (such as Benes networks) and the Omega network. The communication time of the system with faulty processors is minimized by rearranging the order in which the fault-free processors communicate with each other. For any number of faults, a reconfigured system with a general multistage network is shown to require an increase from four to five data transfers for each iteration of the near neighbor problem. For the Omega network, many faults can be handled by six data transfers, but in some cases up to 10 data transfers are necessary. In order to minimize the computation time of the system with faults, the data points of faulty processors are distributed equally and in parallel among the remaining processors. The technique used for parallel data distribution is called Uniform Data Distribution.