Multiplying Digital-to-analog Converter Research Articles

A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC

A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total power dissipation is 42 mW, and it occupies an active chip area of 0.21 mm2 including the calibration circuit. It results in a figure-of-merit (FOM) of 442 fJ/conversion-step. Only 168 clock cycles are used, and no external precise reference sources are needed for the calibration.

A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier

A 10-b 120-MS/s pipeline analog-to-digital converter (ADC) is implemented in a 45 nm CMOS process. Three-stage amplifiers based on reversed nested Miller compensation and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2 Vpp around a 1.6 V common-mode voltage. The prototype ADC with an active die area of 0.58 mm2 consumes 61.6 mW at 120 MS/s and 1.1 V. The measured differential and integral nonlinearities are within ±0.44 and ±0.75 LSB, respectively. At a sampling rate of 120 MHz with a 4.2 MHz sinusoidal input, the measured maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range are 55.6 and 70.4 dB, respectively.

A 12-bit 20 MS/s 56.3 mW Pipelined ADC With Interpolation-Based Nonlinear Calibration

The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage.

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS

This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2 × time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 μm CMOS, shows a resolution of 1.25 ps with a total conversion range of ±160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are ± 0.7 LSB and - 3 to + 1 LSB, respectively.

SHA-less architecture with enhanced accuracy for pipelined ADC

A new design technique for merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) is presented. For reducing the aperture error in the first stage of the pipelined ADC, a symmetrical structure is used in a flash ADC and MDAC. Furthermore, a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC. The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal. The proposed circuit, designed using ASMC 0.35-μm BiCMOS technology, occupies an area of 1.4 × 9 mm2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC. After the trim circuit is enabled, the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration

A 10-b, 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) converts from dc to the 12th Nyquist band with in situ, mostly digital background calibration for the clock skew in the 3.5-b front-end stage. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the front-end sub-ADC to synchronize with that of the sample-and-hold (S/H) in the multiplying digital-to-analog converter (MDAC). The prototype ADC, implemented in a 90-nm CMOS process, digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled (with the default sub-ADC sample point set at the midpoint of the delay range). The prototype with calibration circuits fully integrated on chip consumes 12.2 mW and occupies 0.26-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise and distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit, 50-MS/s pipelined A/D converter (ADC) with proposed area- and power-efficient architecture. The conventional dedicated sample-hold-amplifier (SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter (MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC (SMDAC) architecture, which features low power and stabilization. Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages, in which the effect of opamp offset and crosstalk between stages is decreased. So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB, respectively, with a Nyquist input at full sampling rate. Constant dynamic performance for input frequencies up to 49.7 MHz, which is the twofold Nyquist rate, is achieved at 50 MS/s. The ADC prototype only occupies an active area of 1.81 mm2 in a 0.35 μm CMOS process, and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.

A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-$\mu$m CMOS

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibration is implemented in 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for Coarse ADC (CADC) resolving, and one for residue amplification. A self-timing technique is used to prevent disturbance at the beginning of the residue amplification. The reduction of the MDAC output swing by enhancing the accuracy of CADC increases the output devices' over-drive voltage and decreases output loading. The proposed design methods allow closed-loop MDAC to operate at high speed while maintaining low power consumption. The measured SFDR, SNR, and SNDR are 40.7 dB, 33.8 dB, and 33.7 dB, respectively, at the Nyquist rate input. The ADC power dissipation is 49 mW and corresponds to a figure-of-merit (FoM) of 1.24 pJ/conv.-step. The active area occupies 0.16<formula formulatype="inline"><tex Notation="TeX">$~{\hbox {mm}}^{2}$</tex></formula>. </para>

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18 μm CMOS process, occupies an active area of 2.3 × 1.6 mm2, and consumes 205 mW at 1.8 V.

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57dB at 2MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712LSB. The dynamic range of the ADC is 58.72dB for full-scale input signal at 2MHz input frequency. The ADC consumes 52.6mW at 100MS/s sampling rate. The circuit is implemented using UMC-180nm digital CMOS technology.

A low power cyclic ADC design for a wireless monitoring system for orthopedic implants

This paper presents a low power cyclic analog-to-digital convertor (ADC) design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks (MDACs) and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully optimized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-mum CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution (<12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.

14 bit 50 MS/s 0.18 [micro sign]m CMOS pipeline ADC based on digital error calibration

Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D converter (ADC)-based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while the measured code errors are stored in memory and corrected in the digital domain during normal conversion. The calibration needs the increased power dissipation and chip area of 1.4 and 10.7 , respectively, compared to a 14 bit uncalibrated conventional pipeline ADC. The prototype ADC fabricated in a 0.18 um CMOS process occupies an active die area of 4.2 mm 2 and consumes 140 mW at 1.8 V and 50 MS/s. After calibration, the measured DNL and INL of the ADC are improved from 0.69 to 0.39 LSB and from 33.60 to 2.76 LSB, respectively.

A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 Omega loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.

A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter

The design of 10-bit, 100 MS/s, pipelined analog-to-digital converter (ADC) is presented. A wide-bandwidth and high gain two-stage operational trans-conductance amplifier (OTA) is used in Track-and-Hold Amplifier (THA) and Multiplying Digital-to-Analog Converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range of the circuit. Charge sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kick-back noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the non-linearity error associated with the input signal resulting in a signal to noise distortion ratio of 58.72 dB/57.57 dB @ 2 MHz/ Nyquist frequency respectively. The maximum differential non-linearity (DNL) is +0.6167/ -0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/-0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full scale input signal @ 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm2, which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.