A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

Abstract

This paper describes a 10-bit, 50-MS/s pipelined A/D converter (ADC) with proposed area- and power-efficient architecture. The conventional dedicated sample-hold-amplifier (SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter (MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC (SMDAC) architecture, which features low power and stabilization. Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages, in which the effect of opamp offset and crosstalk between stages is decreased. So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB, respectively, with a Nyquist input at full sampling rate. Constant dynamic performance for input frequencies up to 49.7 MHz, which is the twofold Nyquist rate, is achieved at 50 MS/s. The ADC prototype only occupies an active area of 1.81 mm2 in a 0.35 μm CMOS process, and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.