A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter

Abstract

The design of 10-bit, 100 MS/s, pipelined analog-to-digital converter (ADC) is presented. A wide-bandwidth and high gain two-stage operational trans-conductance amplifier (OTA) is used in Track-and-Hold Amplifier (THA) and Multiplying Digital-to-Analog Converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range of the circuit. Charge sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kick-back noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the non-linearity error associated with the input signal resulting in a signal to noise distortion ratio of 58.72 dB/57.57 dB @ 2 MHz/ Nyquist frequency respectively. The maximum differential non-linearity (DNL) is +0.6167/ -0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/-0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full scale input signal @ 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.