Multiplying Delay-locked Loop Research Articles

A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz.

Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems

This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-μm CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are -204.3, -211.07, -220.29, and -213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively.

A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz.

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the three-stage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO’s period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO’s stages is solved by the proposed dithering-assisted local skew calibration, which removes the skews in the injection path and smears out the periodic pattern at the PLL side to reduce spurs. Most of the dithering noise is suppressed by the injection locking and the phase tracking loop. Measured at 1.0095-GHz output frequency with 24-MHz reference frequency, with the proposed solution, the integrated root-mean-square (rms) jitter can be reduced from 6.40 to 2.55 ps, and the power consumption is 3.36 mW. This translates to −226.6-dB figure of merit (FoM) and −232.8-dB FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> . The measured fundamental fractional spurs range from −56 to −45 dBc.

A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications

ABSTRACT A fully integrated 2-transmitter–4-receiver (2TX–4RX) multiple-input multiple-output (MIMO) radar front-end in the 57–64-GHz band for short-range applications is presented in this paper. The proposed architecture with 8 elements within a one-dimensional virtual array enables theoretical angular resolution down to . The TX chains operate in time-division multiplexing (TDM) mode, and each delivers 12 dBm of saturated output power with output-referred 1-dB compression point (OP1dB) larger than 5 dBm over 7-GHz bandwidth. The millimeter-wave (mm-wave) part of the RX chains has a noise figure lower than 13 dB, and a conversion gain of 17 dB in the 60-GHz unlicensed band. The receiver chain shows a maximum conversion gain of 77 dB, while achieving an input-referred 1-dB compression point (IP1dB) greater than – 12.5 dBm, including baseband circuitry. The programmable baseband processing chain with 60-dB gain allows beat frequency selection in the frequency range from 100 kHz up to 1.3 MHz. Linear chirps are synthesized using a fractional-N phase-locked loop (PLL) with a fundamental voltage-controlled oscillator (VCO). The integrated system includes a programmable multiplying delay-locked loop (MDLL) which scales-up external high purity 40-MHz frequency reference to a referent 240-MHz clock used in the frequency-modulated continuous-wave (FMCW) synthesizer. The front-end is implemented in a 130-nm SiGe:C BiCMOS process. The chip occupies an area of 12 mm2 including pads and consumes 930 mW, combined from 1.2-V and 3.3-V supplies.

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop

An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear approximation and z-domain PN model are utilized to simplify the analysis with excellent agreement between the time-domain simulation and z-domain approximation. The influences of the asymmetric waveform, flicker noise corner, frequency error and reference noise are also discussed and then ignored based on the reasonable approximation. Under a given process, reference clock frequency and supply voltage, the ideal FOM can be derived theoretically. Based on these insights, the predicted FOM can be the benchmark metric in the design of MDLL for the possible best jitter-power performance.

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter =15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 3.56 mW at 1.6 GHz.

A Fractional-N Digital MDLL With Background Two-Point DTC Calibration

This article presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital multiplying delay-locked loop (MDLL) that employs a digital-to-time converter (DTC) to control the reference injection for the fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> operation. The presented MDLL features a background two-point DTC calibration that simultaneously corrects the DTC gain and offset errors to achieve a low-jitter and low-spur architecture. The DTC errors are sensed using an embedded time-to-digital converter (TDC) and extracted in the digital domain for reduced implementation overhead. A new TDC dithering and dither noise cancellation technique is used to improve the estimation accuracy of the DTC errors at the presence of TDC quantization error and differential nonlinearity (DNL). In addition, the adaptive dither noise cancellation scheme uses a comb filter to decouple the dither noise and DTC error estimations, allowing the two schemes to operate simultaneously. The proof-of-concept MDLL prototype fabricated in 65-nm CMOS achieves −60-dBc fractional spur and 1.67-ps rms jitter at around 20-MHz offset. With the proposed calibration scheme, a >25-dB spur reduction in reference and fractional spurs is demonstrated.

A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter

This paper presents a low jitter multiplying delay-locked loop (MDLL) with static phase offset elimination (SPOE) applied to time-to-digital converter (TDC). To reduce static phase offset (SPO) between the reference clock and the output feedback clock, a SPOE techniques based on time amplifier (TA) is proposed, which the reference clock can be accurately injected for timing or phase calibration. The logic selector (LS) used a simplified form to complete mode switching with faster response times. The improved phase detector (PD) implements direct phase discrimination between the output feedback clock and the reference clock. The improved voltage-controlled delay line (VCDL) also makes the MDLL implementing a uniform split-phase output characteristic. The test chip is designed and fabricated in TSMC 0.35-μm 3.3 ​V complementary metal-oxide-semiconductor (CMOS) process which occupies a core area of 0.26 ​mm2. The measurement results show that the output clock jitters at 320 ​MHz frequency is 3.17 ps for root mean square, with the multiplication ratio of 8. The circuit has eight split-phase output clocks with a uniform separation within 45° ​± ​3.4°.

A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS

This article describes a synthesized fractional-N multiplying delay-locked loop (MDLL) implemented in Intel 22-nm FFL FinFET technology. A 2-bit time-period comparator (TPC) is proposed to adjust the ring oscillator frequency to suppress the spurs without introducing errors due to its inherent phase offset. A programmable delay is used to compare the periods of the MDLL output in time domain, reducing power consumption and making the design synthesizable. TPC 2-bit output achieves fast and robust locking without any initial calibration. The fractional multiplication ratio is achieved by using a digital-to-time converter (DTC) in the reference path with a replica of the digitally controlled oscillator (DCO) to automatically achieve a range of one DCO period. Any variation in DTC delay due to gain mismatch is corrected by a digital loop operating in the background. A detailed analysis of the small-signal model and noise of the proposed MDLL has also been presented. The core area of the synthesized design is 0.0052 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while operating over the frequency range from 1.2 to 3.8 GHz. The integrated rms jitter is 2.74 ps, and the spurs are below -47 dBc measured at 3.6175 GHz. Fractional-N MDLL power consumption is 3.19 mW with the figure of merit (FOM) of -226.3 dB.

A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR

A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small area and less power consumption. The shared MDLL generates and distributes eight-phase clocks to each CDR. The proposed CDR uses a new initial phase tracker that uses a preamble to achieve a fast lock time of about 12 ns and to provide a constant output data sequence. The CDR utilizes quarter-rate 2x-oversampling architecture, and the PI controller is designed full custom to minimize the loop latency. To improve the dithering jitter performance of the recovered clock, the decimation factor of the CDR can be adjustable. Also, a new continuous-time linear equalizer (CTLE) receiver was adopted to reduce power consumption and achieved a data rate of 25 Gb/s/lane. The proposed SerDes receiver with a digital CDR is implemented in 40 nm CMOS technology. The 100 Gb/s four-channel SerDes receiver (4 CTLEs + 4 CDRs + MDLL) occupies an active area of only 0.351 mm2 and consumes 241.8 mW, which achieves a high energy efficiency of 2.418 pJ/bit.

A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 μm technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.

A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor

In this brief, a multiplying delay-locked loop (MDLL) using a frequency calibrator (FC) and a voltage monitor (VM) is presented. This FC uses a delay-calibrated subsampling phase detector (SSPD) to reduce the frequency error. The VM is used to cover a wide frequency variation. This MDLL is fabricated in 40-nm CMOS technology. Its active area is 0.013 mm2, and the power consumption is 5.2 mW from a supply of 1 V. It exhibits a root-mean-square jitter of 229 fs at 2.4-GHz output and the reference spur of −54.3 dBc under a reference clock of 150 MHz.

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

This paper presents a novel time-variant model of multiplying delay-locked loops. A simple feed-forward model of the multiplexed ring oscillator mathematically describes the edge realignment process and, by providing an explicit tuning input, allows to be embedded into the time-variant multiplying delay-locked loop model without requiring approximations. Verification of the multiplexed ring oscillator model against detailed circuit simulations is presented. Closed-form expressions for the multiplying delay-locked loop phase noise, as a function of the system parameters and noise sources, are provided.

A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process–voltage–temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digital-controlled delay line (DCDL)-based low-power time-interval comparator and an adjacent-edge selector, to precisely detect the static phase offset (SPO) caused by the VCO frequency drifting in the presence of reference injection. The block-sharing-based SPO detection aids nullifying the circuit-mismatch- and offset-induced deterministic error. Also, for the adjacent edge selector, block sharing between its control generation circuits and the coarse FTL further reduces the power consumption. The varactor-tuned dual multiplexed-ring VCOs (MRVCOs) serve to reduce jitter variation while extending the frequency tuning range. Fabricated in a 28-nm CMOS with a core area of 0.0056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the proposed MDLL covers a tuning range from 1.55 to 3.35 GHz, and exhibits a root-mean-square (rms) jitter of 292 fs at 3-GHz output, under a 200-MHz reference clock. The power consumption is 1.45 mW at a 0.8-V supply, resulting in an FoM of −249 dB favorably comparable with the state of the art.

A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks

This paper presents a 3.52 Gbps low-power 32:1-to-1:32 serializer/deserializer (SerDes) with a multiplying delay-locked loop (MDLL) based frequency multiplier for low-power on-chip serial-link networks. The proposed deserializer adopts a phaseinterpolator (PI)-based 2x-overdampling digital clock and data recovery (CDR) for recovering clock and data signals. The MDLL frequency multiplier provides a multiplication factor of N=16, converting input frequency of 110 MHz into output frequency of 1.76 GHz. Implemented in a 65 nm CMOS process, the proposed SerDes and MDLL perform 32:1 parallel-to-serial multiplexing and 1:32 serial-toparallel de-multiplexing conversion, while achieving a measured data rate of 3.52 Gbps, occupying an active area of 0.19 mm² and dissipating only 14 mW.

Robust high‐multiplication factor MDLL using IIR filter‐based accumulated jitter reduction

A high-multiplication factor multiplying delay-locked loop (MDLL) with infinite impulse response filter-based accumulated jitter reduction technique is presented. In every output clock cycle, the proposed jitter reduction loop samples the periodic jitter, accumulates it, and subtracts accumulated jitter from the next output clock period. The proposed technique is applied to 10 MHz MDLL with 32 kHz reference clock, a multiplication factor of 313, shows 38% jitter reduction, and greatly improves MDLL locking even with high-supply noise. The MDLL implemented in 0.18 μm CMOS process consumes 42 μW and the core area is 0.043 mm 2 .

A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling

A new all-digital multiplying delay-locked loop (MDLL) is presented that can provide programmable fractional-ratio frequency synthesis of a de-skewed clock. The proposed fractional-ratio MDLL (FMDLL) employs a new select logic for controlling three operation modes and utilizes a new phase-detecting structure to achieve inherent cancellation of the internal phase offset. The proposed digital FMDLL is implemented in a 65-nm 1-V CMOS process and occupies an area of 0.019 mm 2 with programmable frequency ratios of N = 1, 4, 5, 8, 10, and M = 1, 2, 3. It operates over a frequency range of 0.7-2.0 GHz and achieves an effective peak-to-peak jitter of 10 ps at 2 GHz when N/M = 8/2. It achieves a locking time of only 40 clock cycles and dissipates 3.3 mW at 1 GHz when N/M = 1/1. The FMDLL employs a new harmonic lock detector to eliminate the harmonic lock problem and achieve dynamic switching of the clock frequencies and division ratios.