A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks

Abstract

This paper presents a 3.52 Gbps low-power 32:1-to-1:32 serializer/deserializer (SerDes) with a multiplying delay-locked loop (MDLL) based frequency multiplier for low-power on-chip serial-link networks. The proposed deserializer adopts a phaseinterpolator (PI)-based 2x-overdampling digital clock and data recovery (CDR) for recovering clock and data signals. The MDLL frequency multiplier provides a multiplication factor of N=16, converting input frequency of 110 MHz into output frequency of 1.76 GHz. Implemented in a 65 nm CMOS process, the proposed SerDes and MDLL perform 32:1 parallel-to-serial multiplexing and 1:32 serial-toparallel de-multiplexing conversion, while achieving a measured data rate of 3.52 Gbps, occupying an active area of 0.19 mm² and dissipating only 14 mW.