Abstract
A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.
Highlights
All‐Digital Clock Generator with aThe high‐frequency on‐chip clock generators used in modern digital system‐on‐chips (SoCs) require the ability to provide dynamic frequency scaling (DFS), which generatesKim, J
As the value of the digital loop filter (DLF) increases according to the output signal (Comp) of the phase detector (PD), the delay of the digital controlled oscillator (DCO) gradually increases, and phase and frequency lock operation start
coarse delay line (CDL) consisting of sixteen serial delay elements (DEs) can have a maximum variable in Figure 5, a clock frequency divider is a circuit that divides thepropagation frequency delay of up to
Summary
The high‐frequency on‐chip clock generators used in modern digital system‐on‐chips (SoCs) require the ability to provide dynamic frequency scaling (DFS), which generates. Among various on-chip clock generators, multiplying delay-locked loops while (MDLLs) improving the jitter performance reducedthe loop bandwidth issues [4,5,6,7,8,9,10,11,12,13,14,15,16]. This structure can generate fully de‐skewed N/M‐ratio frequency frequencyusing multiplication using a 3-to-1 a new structure phase detecting structure multiplication a 3‐to‐1 MUX and a newMUX phaseand detecting that directly re‐ that directly receives as inputs of the PD. The residual phase error becomes zero, and the lock state At this time, the residual phase error becomes zero, and the output frequency output frequency has a fractional ratio value multiplied by N/M = 5/2.
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