Multiply-and-accumulate Operations Research Articles

Investigation into designing VLSI of a flexible architecture for a deep neural network accelerator

Deep learning, a branch of AI, makes use of specialised neural networks. Computational acceleration of high-performance deep neural network algorithms continues to necessitate efficient architecture, high memory bandwidth, parallel processing, and resources, despite decades of study on such algorithms. Excessive space requirements are a problem for DNN implementations caused by resource-intensive components like activation functions (AF) and multiply-and-accumulate (MAC) units. In addition, edge-AI applications necessitate a densely packed, power-hungry, high-throughput DNN accelerator. If we want to build a DNN accelerator that uses little power and occupies little space, we need to optimise the MAC architecture, the AF, and the network complexity so that data flows efficiently. In addition, providing functional configurability while working with restricted chip surface is a difficulty for DNN hardware designs based on ASICs. This dissertation explores the efficient and low-power VLSI architecture of DNN accelerators, addressing the hardware implementation of DNN and targeting applications with limited resources. In order to assess MAC and non-linear AF operations, we investigate and enhance the CORDIC architecture. The poor throughput is a major downside of CORDIC-based architectures, even though they are area and power efficient. Consequently, we suggest a pipelined design for CORDIC-based MAC and AF that focuses on performance. Due to the increased hardware resource consumption that comes with pipeline stages, this study investigates the mutual exclusivity of CORDIC stages and investigates in depth the accuracy variation related to the number of stages needed to achieve high throughput.

High energy efficient and configurable CIM macro for image processing

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W.

A nanosecond-scale CuI synaptic memristor prepared by a solution-based process

Owing to the synaptic behaviors and functions, memristors are intensively studied as a critical component for the neuromorphic computing system which is considered as an effective scenario to tackle the performance bottleneck existing in modern computers based on the von Neumann architecture. A novel synaptic device base on the CuI memristor prepared with a solution-based process is proposed in this work, and a set of synaptic features are emulated. The electrochemical metallization contributes to the resistive switching behavior and small operating voltages (Vset = 0.67 V and Vreset = −0.33 V). Moreover, the CuI memristor exhibits the small switching energy (23 pJ) and ultraquick switching speed (100 ns). A large CuI memristor array is realized experimentally, by which the hardware-based multiply-and-accumulate (MAC) operation is implemented. Furthermore, the hardware-based convolution computation in image processing is realized based on the MAC operation, demonstrating the potential applications in image processing requiring the high degree of parallelism.

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb.

In‐memory multibit multiplication and accumulation based on an automatic pulse generation circuit

AbstractComputing‐in‐memory (CIM) is a promising technique for solving the ‘memory wall’ and ‘power consumption wall’ problems. However, calculations in the analog domain are limited in terms of accuracy and sensitivity to process, voltage, and temperature changes. In this study, the authors proposed a CIM multiply‐and‐accumulate (MAC) circuit in which the MAC result was reflected by the pulse edge and converted into the final digital output using a dual‐edge counter quantization circuit, thereby improving the accuracy of the MAC operation and reducing the difficulty of quantization. The performance of the proposed CIM circuit was evaluated using a 28‐nm process. It could achieve 4‐bit multiplication without errors, with an energy efficiency of 24.38 to 670.86 TOPS/W.

PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing

With the rapid development of the Internet of Things (IoT), compute-in-memory (CIM) is a promising candidate for edge computing, which eliminates the need for frequent data transfer between the memory and processing units. On one hand, CIM provides an efficient approach to achieve deep neural network (DNN) inference; on the other hand, its security issues such as model leakage are ignored in most of state-of-the-art studies. In the resource-limited conditions, it is essential to develop a lightweight secure scheme for CIM without significantly sacrificing its performance. In this work, a physical unclonable function (PUF)-CIM macro based on static random access memory (SRAM) is proposed for lightweight model protection. An SRAM-based PUF extracts unique and stable keys from the mismatch of multirow discharge rate and further achieves zero bit error rate (BER) under temperature and voltage fluctuations by the on-chip masking technique. Besides, we propose a 10T SRAM bit cell to perform xor operation and multiply-and-accumulate (MAC) operation in the same cell, which avoids weight movement during encryption and decryption. The whole process including key generation, xor encryption, and ciphertext MAC operation has been realized. The test chip is designed and fabricated in a 55-nm CMOS process. Experimental results show that the proposed PUF with on-chip masking can provide zero unstable bits and BER under temperature and voltage variations. The proposed PUF-CIM achieves 96.20% inference accuracy in MNIST. Besides, it presents 93.35–121.38-TOPS/W energy efficiency and 1324.24-GOPS throughput. Compared with the normal CIM, the proposed PUF-CIM can enhance AI model security, only with accuracy loss of 1% and energy efficiency degradation of 16.1%.

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization

Computing-in-memory (CIM) is an attractive approach for energy-efficient deep neural network (DNN) processing, especially for low-power edge devices. However, today’s typical DNNs usually exceed CIM-static random access memory (SRAM) capacity. The introduced off-chip communication covers up the benefits of CIM technique, meaning that CIM processors still encounter the memory bottleneck. To eliminate this bottleneck, we propose a CIM processor, called TT@CIM, which applies the tensor-train decomposition (TTD) method to compress the entire DNN to fit within CIM-SRAM. However, the cost of storage reduction by TTD is to introduce multiple serial small-size matrix multiplications, resulting in massive inefficient multiply-and-accumulate (MAC) and quantization operations (QuantOps). To achieve high energy efficiency, three optimization techniques are proposed in TT@CIM. First, TTD-CIM-matched dataflow is proposed to maximize CIM utilization and minimize additional MAC operations. Second, a bit-level-sparsity-optimized CIM macro with high bit-level-sparsity encoding scheme is designed to reduce the power consumption of one MAC operation. Third, a variable precision quantization method and a lookup table-based quantization unit are presented to improve the performance and energy efficiency of QuantOp. Fabricated in 28-nm CMOS and tested on 4/8-bit decomposed DNNs, TT@CIM achieves 5.99-to-691.13-TOPS/W peak energy efficiency depending on the operating voltage.

Adaptive pooling-based convolution factorization for deploying CNNs on energy-constrained IoT edge devices

Convolutional neural networks (CNNs) involve a tremendous amount of multiply-and-accumulate (MAC) computations, leading to energy issues when deployed on energy-constrained IoT edge devices for computer vision purposes. However, a great number of these computations are ineffectual since they lead to meaningless zero activations, which could be avoided if predicted appropriately. This has been the focus of many studies, whereas it has only been done through zero-activation simplifications. This paper goes beyond those simplifications through a convolution factorization approach to convert the MAC-intensive convolution operations into less complex pooling operations. The main characteristic of the proposed idea is that, given a target accuracy, the applicability and type of factorization are adaptively decided for each individual activation. This is achieved by providing a lightweight multi-class CNN-based predictor, namely RedZAP. The selected types of pooling operations for our convolution factorizations are supported by existing CNN architectures. The experimental results show that, given a top-1 accuracy loss constraint of 1%, the proposed approach saves another 8% MAC operations in comparison to the existing zero-prediction approaches in the literature.

Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture

Deep neural networks (DNNs) require abundant multiply-and-accumulate (MAC) operations. Thanks to DNNs' ability to accommodate noise, some of the computational burden is commonly mitigated by quantization – that is, by using lower precision floating-point operations. Layer granularity is the preferred method, as it is easily mapped to commodity hardware. In this paper, we propose Dynamic Asymmetric Architecture (DAA), in which the micro-architecture decides what the precision of each MAC operation should be during runtime. We demonstrate a DAA with two data streams and a value-based controller that decides which data stream deserves the higher precision resource. We evaluate this mechanism in terms of accuracy on a number of convolutional neural networks (CNNs) and demonstrate its feasibility on top of a systolic array. Our experimental analysis shows that DAA potentially achieves 2x throughput improvement for ResNet-18 while saving 35% of the energy with less than 0.5% degradation in accuracy.

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices

Compute-in-memory (nvCIM) macros based on non-volatile memory make it possible for artificial intelligence (AI) edge devices to perform energy-efficient multiply-and-accumulate (MAC) operations by minimizing the movement of data between the processors and memory. However, nvCIM imposes tradeoffs between energy efficiency, computing latency, and readout accuracy against process variation. To overcome these challenges, this work proposed a nvCIM macro featuring: 1) a direct-current-free time-space-based in-memory computing (DCFTS-IMC) scheme; 2) a wordline-based serial access computing (WSAC) scheme; 3) an integration-based voltage-to-time converter (IVTC); and 4) a hidden-latency time-to-MAC value conversion (HLTMC) scheme. The proposed 22-nm 8-Mb resistive random access memory-CIM (ReRAM-CIM) macro was fabricated to demonstrate MAC operations with 8-b input, 8-b weight, and 19-b output. Our nvCIM macro achieved computing latency of 14.4 ns under 8-b precision with an energy efficiency of 21.6 TOPS/W.

A Nonvolatile All-Spin Nonbinary Matrix Multiplier: An Efficient Hardware Accelerator for Machine Learning

We propose and analyze a compact and non-volatile nanomagnetic (all-spin) non-binary matrix multiplier performing the multiply-and-accumulate (MAC) operation using two magnetic tunnel junctions - one activated by strain to act as the multiplier, and the other activated by spin-orbit torque pulses to act as a domain wall synapse that performs the operation of the accumulator. It has two advantages over the usual crossbar-based electronic non-binary matrix multiplier. First, while the crossbar architecture requires N3 devices to multiply two matrices, we require only 2N2 devices. Second, our matrix multiplier is non-volatile and retains the information about the product matrix after being powered off. Here, we present an example where each MAC operation can be performed in ~5 ns and the maximum energy dissipated per operation is ~60Nmax aJ, where Nmax is the largest matrix size. This provides a very useful hardware accelerator for machine learning and artificial intelligence tasks which involve the multiplication of large matrices. The non-volatility allows the matrix multiplier to be embedded in powerful non-von-Neumann architectures, including processor-in-memory. It also allows much of the computing to be done at the edge (of internet-of-things) while reducing the need to access the cloud, thereby making artificial intelligence more resilient against cyberattacks.

FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems

With the widespread of deep neural networks (DNNs) in diverse applications, tiny platforms such as Internet-of-Things devices are starting to adopt DNNs. Due to their extreme energy and form factor constraints, conventional digital-only implementations of multiply-and-accumulate (MAC) acceleration faced fundamental limitations. To that end, the investigation into mixed-signal computing architectures is growing rapidly. Motivated by the flash ADC, this article proposes FlashMAC architecture that can natively support multibit multiplication. In addition, through fusing time- and frequency-domain computing methods without power-hungry oscillators, it enables low latency accumulation with low power consumption. As a result, the proposed time-frequency hybrid architecture achieves high energy efficiency with the support for complex DNN models requiring higher precision. To enhance the robustness of PVT variation of the mixed-signal architecture, a frequency calibration loop is integrated. In addition, motivated by the data-dependent performance of the FlashMAC architecture, variable latency-aware scheduling is proposed. The FlashMAC does not skip MAC operations as zero-skipping architectures do, but the latency of the operation can be lower when operands are smaller in magnitude. Tackling the issue through software and hardware co-optimization, loose synchronization architecture and magnitude-aware weight reordering increase the DNN benchmark performance by achieving higher utilization of the parallel FlashMAC array. The proposed features are integrated into a test chip which is fabricated in 65-nm logic CMOS technology. The silicon chip achieves 56.52 TOPS/W peak energy efficiency and a peak operating frequency of 90 MHz. Tested with the VGG16 benchmark trained on the Imagenet dataset, it achieved 17.04-ms latency while showing 11.15 TOPS/W energy efficiency. As a result, compared to the previous state-of-the-art, the proposed FlashMAC achieved 3.15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> higher normalized energy efficiency.

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications

In this work, we present a 6T SRAM computing-in-memory(CIM) macro in robust charge domain using (1) a local process element with digital-to-analog-converter-less input for eliminating non-linear and variation caused by multi-bit input, supporting XNOR and AND operations, (2) an in-memory 4-bit weight accumulation scheme for multiply-and-accumulate (MAC) operation, to reduce energy cost and achieve area-compact design, (3) a reconfigurable prioritized subranging analog-to-digital-converter for energy saving, supporting a 4-b or 4 2.24-b quantizations for multi-mode operations. The proposed design support AND and XNOR MAC operations. With a layout implementation in 28 nm CMOS process, the 128 kb SRAM CIM macro achieves good computing linearity and variation. The array area efficiency is 76.63%. The average energy efficiency is 175.2 TOPS/W while performing AND mode MAC with 2-b input and 4-b weight, and is 1379.4 TOPS/W in XNOR mode MAC. The behavioral simulation shows a classification accuracy of 85.55% in CIFAR-10. The average accuracy loss is only 1.37% compared with the software baseline.

Photonic neuromorphic computing using vertical cavity semiconductor lasers

Photonic realizations of neural network computing hardware are a promising approach to enable future scalability of neuromorphic computing. The number of special purpose neuromorphic hardware and neuromorphic photonics has accelerated on such a scale that one can now speak of a Cambrian explosion. Work along these lines includes (i) high performance hardware for artificial neurons, (ii) the efficient and scalable implementation of a neural network’s connections, and (iii) strategies to adjust network connections during the learning phase. In this review we provide an overview on vertical-cavity surface-emitting lasers (VCSELs) and how these high-performance electro-optical components either implement or are combined with additional photonic hardware to demonstrate points (i-iii). In the neurmorphic photonics context, VCSELs are of exceptional interest as they are compatible with CMOS fabrication, readily achieve 30% wall-plug efficiency, &gt;30 GHz modulation bandwidth and multiply and accumulate operations at sub-fJ energy. They hence are highly energy efficient and ultra-fast. Crucially, they react nonlinearly to optical injection as well as to electrical modulation, making them highly suitable as all-optical as well as electro-optical photonic neurons. Their optical cavities are wavelength-limited, and standard semiconductor growth and lithography enables non-classical cavity configurations and geometries. This enables excitable VCSELs (i.e. spiking VCSELs) to finely control their temporal and spatial coherence, to unlock terahertz bandwidths through spin-flip effects, and even to leverage cavity quantum electrodynamics to further boost their efficiency. Finally, as VCSEL arrays they are compatible with standard 2D photonic integration, but their emission vertical to the substrate makes them ideally suited for scalable integrated networks leveraging 3D photonic waveguides. Here, we discuss the implementation of spatially as well as temporally multiplexed VCSEL neural networks and reservoirs, computation on the basis of excitable VCSELs as photonic spiking neurons, as well as concepts and advances in the fabrication of VCSELs and microlasers. Finally, we provide an outlook and a roadmap identifying future possibilities and some crucial milestones for the field.

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices

Compute-in Memory (CIM) has been a promising candidate to perform the energy-efficient multiply-and-accumulate (MAC) operations of the modern Artificial Intelligence (AI) edge devices. This work proposes a multi-bit precision (4b input, 4b weight, and 4b output) 128 × 128 SRAM CIM architecture. The 4b input is implemented using the voltage-scaling and charge-sharing-based scheme. To achieve efficient computation with improved linearity, a novel AND-logic-based 8T SRAM cell (AND8T) is proposed. To address the non-idealities of analog voltage or current-based operations, the proposed AND8T employs the charge-domain-based computation by overlaying a metal-oxide-metal capacitor (MOM cap) with no area overhead. The proposed AND8T mitigates the linearity issue of MAC operations which is highly desirable for the reliable operation of complex neural networks (CNNs). The proposed 16Kb macro asserts 128 inputs in parallel and processes a 128 4b dot-product in a single cycle for the array column (a single neuron). The macro can also be reconfigured for the 64 or 32 4b parallel inputs based on the need of CNN models. The AND8T SRAM macro is fabricated in a 65nm node and achieves an energy efficiency of 301.08 TOPS/W for 16 parallel neurons output, with 128 4b MAC operations at 10MHz clock frequency and 1V supply. The implemented macro supports up to 100MHz of clock frequency and occupies 0.124mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area while achieving the 96.05% and 87% classification accuracy for MNIST and CIFAR-10 datasets.

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization

Accelerators for convolutional neural networks (CNNs) based on field-programmable gate arrays (FPGAs) have drawn much attention in recent years. Two INT-8 multiplications are often implemented on a single digital signal processor (DSP) to improve DSP efficiency and performance. However, most of these works only use DSPs to implement multiplications and do not involve accumulations, which requires a lot of look-up tables (LUTs) and consequently leads to greater energy consumption. Furthermore, these works do not detail how to obtain two signed INT-8 multiplications with a DSP. This brief thus proposes a tiny accelerator for CNNs and a DSP-based processing element (PE) that is designed to implement two signed INT-8 multiply-and-accumulate (MAC) operations to reduce the overhead of LUTs. To allow the DSP to support two signed INT-8 MAC operations and avoid the large loss of accuracy caused by data overflow of partial sums (psum), we apply an efficient DSP optimization approach and a dynamic-precision quantization method. The accelerator is implemented on a Xilinx ZC706 FPGA device and achieves a DSP utilization efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.3\times $ </tex-math></inline-formula> greater than state-of-the-art accelerators implemented on the same device. Furthermore, our accelerator offers <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.56\times $ </tex-math></inline-formula> greater energy efficiency than other FPGA-based accelerators.

Scaling up silicon photonic-based accelerators: Challenges and opportunities

Digital accelerators in the latest generation of complementary metal–oxide–semiconductor processes support, multiply, and accumulate (MAC) operations at energy efficiencies spanning 10–100 fJ/Op. However, the operating speed for such MAC operations is often limited to a few hundreds of MHz. Optical or optoelectronic MAC operations on today’s SOI-based silicon photonic integrated circuit platforms can be realized at a speed of tens of GHz, leading to much lower latency and higher throughput. In this Perspective, we study the energy efficiency of integrated silicon photonic MAC circuits based on Mach–Zehnder modulators and microring resonators. We describe the bounds on energy efficiency and scaling limits for N × N optical networks with today’s technology based on the optical and electrical link budget. We also describe research directions that can overcome the current limitations.

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Computing-in-memory (CIM) based on SRAM is a promising approach to achieving energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices; however, existing SRAM-CIM chips support only DNN inference. The flow of training data requires that CIM arrays perform convolutional computation using transposed weight matrices. This article presents a two-way transpose (TWT) multiply cell with high resistance to process variation and a novel read scheme that uses input-aware zone prediction of maximum partial MAC values to enhance the signal margin for robust readout. A 28-nm 64-kb TWT CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {AC}}$ </tex-math></inline-formula> of 3.8–21 ns and energy efficiency of 7–61.1 TOPS/W in performing MAC operations using 2–8-b inputs, 4–8-b weights, and 10–20-b outputs.

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection

Computing-in-memory (CIM) architectures have gained importance in achieving high-throughput energy-efficient artificial intelligence (AI) systems. Resistive RAM (RRAM) is a promising candidate for CIM architectures due to a multiply-and-accumulate (MAC)-friendly structure, high bit density, compatibility with a CMOS process, and nonvolatility. Notwithstanding the advancement of RRAM technology, the reliability of an RRAM array hinders the spread of RRAM applications such that a circuit-technology joint approach is necessary to attain reliable RRAM-based CIM architectures. This article presents a 64-kb hybrid CIM/digital RRAM macro supporting: 1) active-feedback-based voltage-sensing read (RD) to enable 1–8-b programmable vector-matrix multiplication under a low-resistance ratio of the high-resistance state to the low-resistance state in an RRAM array; 2) iterative write with verification to secure a tight resistance distribution; and 3) online RD-disturb detection in the background during CIM. The test chip fabricated in a 40-nm CMOS and RRAM process achieves a peak energy efficiency of 56.67 TOPS/W while demonstrating the eight-bitline hybrid CIM/digital MAC operation with 1–8-b inputs and weights and 20-b outputs without quantization.

A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8-b weight to 119.2 TOPS/W for 2-b weight.