Multiple Implementations Research Articles

FPGA‐Based Resource‐Optimal Approximate Multiplier for Error‐Resilient Applications

ABSTRACTArithmetic units inspired by approximate computations have seen a significant development in error‐resilient applications, wherein accuracy can be traded off for enhanced performance. Most of the existing literature pertaining to approximate computations targets ASIC platforms. In this paper, we focus on exploiting the features of approximate computation to design efficient digital hardware for FPGA platforms. Specifically, we propose an FPGA implementation of an approximate multiplier unit based on the CORDIC algorithm. Contemporary FPGA‐based approximate multiplier implementations report a lot of compromise in accuracy and a relatively higher implementation cost in terms of utilized resources, timing, and energy. We conduct a detailed Pareto analysis to determine the number of optimal computing stages for the proposed CORDIC‐based approximate multiplier that justifies the accuracy‐performance trade‐offs. More importantly, we focus on the optimal logic distribution of the proposed multiplier circuit by restructuring the top‐level Boolean network and translating it into a circuit netlist that can be efficiently mapped onto the inherent FPGA fabric of LUTs and Carry4 primitives. Our CORDIC‐based implementations significantly improve the accuracy metrics while maintaining a suitable performance trade‐off. The efficacy of our proposed multiplier is tested using two image‐processing applications, namely, image blending and image smoothening. The obtained results show a substantial improvement over the existing state‐of‐the‐art approximate multipliers.

A High-performance NTT/MSM Accelerator for Zero-knowledge Proof Using Load-balanced Fully-pipelined Montgomery Multiplier

Zero-knowledge proof (ZKP) is an attractive cryptographic paradigm that allows a party to prove the correctness of a given statement without revealing any additional information. It offers both computation integrity and privacy, witnessing many celebrated deployments, such as computation outsourcing and cryptocurrencies. Recent general-purpose ZKP schemes, e.g., zero-knowledge succinct non-interactive argument of knowledge (zk-SNARK), suffer from time-consuming proof generation, which is mainly bottlenecked by the large-scale number theoretic transformation (NTT) and multi-scalar point multiplication (MSM). To boost its wide application, great interest has been shown in expediting the proof generation on various platforms like GPU, FPGA and ASIC.So far as we know, current works on the hardware designs for ZKP employ two separated data-paths for NTT and MSM, overlooking the potential of resource reusage. In this work, we particularly explore the feasibility and profit of implementing both NTT and MSM with a unified and high-performance hardware architecture. For the crucial operator design, we propose a dual-precision, load-balanced and fully-pipelined Montgomery multiplier (LBFP MM) by introducing the new mixed-radix technique and improving the prior quotient-decoupled strategy. Collectively, we also integrate orthogonal ideas to further enhance the performance of LBFP MM, including the customized constant multiplication, truncated LSB/MSB multiplication/addition and Karatsuba technique. On top of that, we present the unified, scalable and highperformance hardware architecture that conducts both NTT and MSM in a versatile pipelined execution mechanism, intensively sharing the common computation and memory resource. The proposed accelerator manages to overlap the on-chip memory computation with off-chip memory access, considerably reducing the overall cycle counts for NTT and MSM.We showcase the implementation of modular multiplier and overall architecture on the BLS12-381 elliptic curve for zk-SNARK. Extensive experiments are carried out under TSMC 28nm synthesis and similar simulation set, which demonstrate impressive improvements: (1) the proposed LBFP MM obtains 1.8x speed-up and 1.3x less area cost versus the state-of-the-art design; (2) the unified accelerator achieves 12.1x and 5.8x acceleration for NTT and MSM while also consumes 4.3x lower overall on-chip area overhead, when compared to the most related and advanced work PipeZK.

Adaptive prairie dog optimization based variable length conditional counter for designing multiplier

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.

A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation

Since multiplication is a complex and resource-consuming operation, it is very effective on the speed performance of a processor. In this regard, fast multiplication unit design is important in digital system architectures. FPGA hardware, which is efficient for the implementation and rapid prototyping of today’s digital system architectures, is becoming widespread. Therefore, in this study it aimed to design a fast radix-16 Booth multiplier based on the FPGA architecture. Booth multiplier implementation is preferred because it is relatively simple and efficient. The sizes of the multiplexers, which have an impact on the operating period in the encoder part of the proposed multiplier, reduced in the designed architecture by using a simple algorithm. To increase the speed performance of the system, the pipeline technique is used and parallelization is preferred in the tree structure in addition of the partial products. The effects of different multiplexer sizes, bit lengths and pipeline stages on the operating period of the system and other performance metrics examined. Different designs and the results obtained presented. According to the results, the multiplier hardware architectures designed in this study exhibit effective results in terms of speed performance.

Design and implementation of a nano-scale high-speed multiplier for signal processing applications

Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.

Design and Implementation of a Wide-Swing CMOS Multiplier for AC Source Signal Tracking and Modulation

Design and Implementation of a Wide-Swing CMOS Multiplier for AC Source Signal Tracking and Modulation

16-Bit multiplier optimization based on Wallace tree and Booth algorithm

With the expanding computer application scenarios and increasing computational demands, optimizing 16-bit multiplication is an important and meaningful research topic. In this paper, we take advantage of the parallel computing property of Wallace tree and the advantage of bit-level operation of Booth algorithm to perform certain optimization on 16-bit multiplier. In this paper, a series of basic modules are firstly constructed as the basic framework of the multiplier, and then the optimization module is designed by using Booth algorithm and Wallace tree, and they are combined to obtain a multiplier with improved computational accuracy, reduced computational complexity, reduced delay, and improved computational efficiency compared with the traditional multiplier. The significance of the optimized multiplier implementation is to increase the computational speed, improve the chip resource utilization, reduce the power consumption and energy consumption, and meet the demand of complex applications, which is of great significance to improve the performance and efficiency of computer systems.

ЭКОНОМИЧЕСКАЯ СУЩНОСТЬ МУЛЬТИГОЛОСУЮЩИХ АКЦИЙ И ВОЗМОЖНОСТЬ ИХ ИМПЛЕМЕНТАЦИИ НА РОССИЙСКОМ ФИНАНСОВОМ РЫНКЕ

Entrepreneurs often encounter challenges related to capital dilution and diminished control over strategic development when forming equity capital. The author proposes the adoption of multiple voting shares as a potential solution to this problem. It has been disclosed that a joint-stock company can issue multiple voting shares at various stages of its life cycle. The circulation of these shares is limited due to their conversion into ordinary shares during purchase and sale transactions, or in case of a specified duration of circulation prohibition. The implementation of a voting multiplier has been announced; clarifying that possessing multiple voting shares does not entitle the owner to extra dividend payments. Conversely, multiple voting shares are transformed into common shares at a one-to-one ratio determined by market value. The result of the study of the economic essence of multiple voting shares was the identification and analysis of the option component of this security. Therefore, there exists the potential to adopt an innovative method of generating financing opportunities for the company by introducing multiple voting shares that encompass the advantages of ordinary shares and a derivative financial instrument. Given the current state of the Russian financial market, where multiple voting shares are exclusively accessible to international companies, the author has developed proposals to modify the existing Russian legislation. These modifications will enable the standardization of equity formation practices among Russian joint-stock companies, while also enhancing the investment appeal of the Russian market for investors from allied states, where the trading of multiple voting shares is permitted.

Design and implementation of wallace tree multiplier and its applications in FIR filter

Limited Drive Reaction channels are the most significant component in signal handling and correspondence. The architecture of a FIR filter includes a delay unit, multiplier, and adder. Along these lines, execution of FIR channel is chiefly founded on multiplier. This paper presents FIR filter execution of the Wallace multiplier. Delay, power, and area performance can all be improved with this method. VHDL is used to write the code, which is simulated using ModelSim 6.3c and synthesized using Xilinx ISE 9.2i. The design is then implemented in the Spartan-3 FPGA.

High-Performance Implementation of a 1024-bit Full-Word Montgomery Modular Multiplier for High-Speed Encryption Hardware Circuit

High-Performance Implementation of a 1024-bit Full-Word Montgomery Modular Multiplier for High-Speed Encryption Hardware Circuit

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier

A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier

High-performance unified modular multiplication algorithm and hardware architecture over G(2m)

The finite field Modular Multiplier (MM) over GF (2m) based on the National Institute of Standards and Technology (NIST) recommended polynomials can be used as a critical component in many cryptosystems. But much of the research suffers from the problems of only supporting a single curve or being very inefficient. In this paper, we present a KA-based unified algorithm (hybrid field size) and its corresponding architecture for high-performance implementation of the systolic modular multiplier over GF (2m), which can support all the NIST recommended polynomials. A number of efficient techniques have been explored and used to realize a high-performance implementation of the multiplier. First, we propose a three-term KA based MM approach and make it fit for systolic implementation. Second, we propose a configurable, unified irreducible polynomial that can support all five curves recommended by NIST and the corresponding modular reduction method. Third, the corresponding systolic structure is also designed in accordance with (1) and (2) to improve efficiency, and we adopt register sharing and computation unit sharing methods to reduce the space complexity of the proposed structure. Additionally, parallel computation of two163-width MMs is employed to improve resource utilization further. From the synthesis results on ASIC, it is shown that the proposed multipliers have significantly lower latency and higher performance than the existing designs. e.g., the proposed structure could achieve up to a 73 % reduction in area-delay product (ADP) over the existing structures.

Design and Implementation of Hybrid Multiplier for DSP Applications

In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit. The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS.

Design of integrated voltage multipliers using standard CMOS technologies

Results of the design of the integrated multistage voltage multipliers as components of supply modules for wireless passive microdevices are presented. Parameters of MOS transistors significant for the multipliers design and presented in three standard CMOS technologies, CM018G 180 nm, HCMOS8D 180 nm and C250G 250 nm, are considered. CAD Cadence simulation results have demonstrated that in the case of eight-stage multiplier implementation using CM018G technology minimum output voltage level requisite for microchip operation is achieved at input amplitude 250 mV and in the case of the similar device implementation using HCMOS8D technology - at 375 mV. Using sixteen-stages multiplier as example it is shown that voltage multiplication efficiency is from 20% to 54% for wide range of the input voltage, and the efficiency decreases only by 1-3% compared to eight-stage implementation. Proposed recommendations for the integrated voltage rectifiers-multipliers design could be applied at development of the passive supply units for microelectronic devices.

Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA

Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

Implementation of Efficient Vedic Multiplier and Its Performance Evaluation

The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm.

High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA

Saber was once one of the most promising candidates for the post-quantum cryptography standardization, which relies on lattice-based hard mathematical problems. Polynomial multiplication is time-consuming within the Saber architecture and there is still a lack of designs targeting the high throughput applications whose parameters support Schoolbook polynomial multiplier. In this brief, we propose a high-performance Schoolbook polynomial multiplier with a balanced hardware efficiency. The Schoolbook algorithm is transformed into a Toeplitz matrix-vector product, and its symmetry is exploited to reconstruct the Schoolbook multiplier to satisfy the need for high parallelism. Combined with compact data loading structure and a centralizing multiplication, the multiplier achieves 3.33× higher throughput and 1.58× higher throughput-per-slice compared with the state-of-the-art implementation of polynomial multiplier for Saber on Xilinx FPGA. The experimental results also demonstrate that the proposed structure provides a better trade-off between performance and area.

Synthesis of Modular Multipliers

The results of experiments on the circuit implementation of modular multipliers in the design library of ASIC (Application-Specific Integrated Circuits) and FPGA (Field-Programmable Gate Array) are presented. The initial descriptions of modular multiplier projects were given by systems of not fully defined (partial) Boolean functions and algorithmic VHDL descriptions. Logical optimization was carried out in the class of disjunctive normal forms (DNF) and representations of Boolean function systems by BDD (Binary Decision Diagrams). The synthesized circuits were evaluated by area and time delay. It is established that the use of partial Boolean function models and preliminary logi­cal BDD optimization allows one to improve the parameters of synthesized ASIC and FPGA blocks for small module values, however, the best solutions for large module values can be obtained using algorithmic VHDL descriptions of modular multipliers. In the synthesis of modular multiplier circuits as part of an FPGA and the use of ISE and Vivado design systems it is advisable to use synthesized VHDL operations (a*b) mod p.

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.