Multiple Implementations Research Articles

Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier

We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.

Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography

Problem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not dissipate any energy. If reversible circuits are used, then the attacker would not be able to analyze the power consumption. In order to design the reversible ALU of a crypto-processor, reversible Carry Save Adder (CSA) using Modified TSG (MTSG) gates and architecture of Montgomery multiplier were proposed. For reversible implementation of Montgomery multiplier, efficient reversible multiplexers and sequential circuits such as reversible registers and shift registers were presented. Results: This study showed that modified designs perform better than the existing ones in terms of number of gates, number of garbage outputs and quantum cost. Lower bounds of the proposed designs were established by providing relevant theorems and lemmas. Conclusion: The application of reversible circuit is suitable to the field of hardware cryptography.

All-pass optical structures for repetition rate multiplication

We propose and analyze several simple all-pass spectrally-periodic optical structures, in terms of accuracy and robustness, for the implementation of repetition rate multipliers of periodic pulse train with uniform output train envelope, finding optimum solutions for multiplication factors of 3, 4, 6, and 12.

Four-quadrant analog multiplier based on CMOS inverters

In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with digital CMOS, since there are only two transistors stacked-up between supply rails. Thus the supplying voltage of this circuit class is the lowest possible one for any particular CMOS technology. The operation principle based on symbolic analysis with simple square model has been fully confirmed by simulations with BSIM3v3 models provided by different silicon foundries and verified experimentally using one of them.

Multiplier Evolution: A Family of Multiplier VLSI Implementations

This paper provides an overview of four floating point multiplier implementations spanning microprocessor designs from 1992 to the present. The algorithm of each multiplier is explored in detail, and key measures of area, delay and design complexity are compared. The approaches span from a simple linear array to a full tree-based network, each targeted at efficient very-large-scale integration implementation. The designs show a progression of implementation techniques encompassing a 20× increase in multiplier performance during this time period.

FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design

Binary-coded decimal digit multipliers

With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi- and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations.

Efficient FPGA implementation of bit-stream multipliers

A four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables

Design and implementation of a high-speed matrix multiplier based on word-width decomposition

This paper presents a flexible 2/spl times/2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. An energy reduction mechanism is incorporated in the architecture to minimize the power dissipation due to unnecessary switching of logic. Two types of decomposition schemes are discussed, which support 2's complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. We provide results on performance of the proposed architecture from FPGA post-synthesis results. We summarize design factors influencing the overall execution speed and complexity.

Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs

Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs

Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2 m ) Generated by AOPs

Galois fields GF(2m) are used in modern communication systems such as computer networks, satellite links, or compact disks, and they play an important role in a wide number of technical applications. They use arithmetic operations in the Galois field, where the multiplication is the most important and one of the most complex operations. Efficient multiplier architectures are therefore specially important. In this paper, a new method for multiplication in the canonical and normal basis over GF(2m) generated by an AOP (all-one-polynomial), which we have named the transpositional method, is presented. This new approach is based on the grouping and sharing of subexpressions. The theoretical space and time complexities of the bit-parallel canonical and normal basis multipliers constructed using our approach are equal to the smallest ones found in the literature for similar methods, but the practical implementation over reconfigurable hardware using our method reduces the area requirements of the multipliers.

Research and Implementation of a 32-Bit Asynchronous Multiplier

Research and Implementation of a 32-Bit Asynchronous Multiplier

A radix-4 scalable design

Modular arithmetic operations are very important in cryptography. Modular multiplication is the most common arithmetic operation used in many cryptographic algorithms such as the Elliptic Curve Cryptography and the Diffie-Helman key exchange. The Montgomery Modular Multiplication algorithm (MM) has permitted cryptographic algorithms to speed up considerably. Multiplication is implemented by a series of multiprecision partial-product addition. The proposed multiple-word Radix-4 Montgomery Multiplication algorithm (R4MM) is extension of the Multiple-Word High-Radix (R2/sup k/) Montgomery Multiplication algorithm (MWR2/sup k/MM). There are two types of recoding applied in the R4MM. The architecture of the modular multiplier that implements the R4MM consists of three main blocks: the datapath (or kernel), the IO & memory and the control block. The computation in the R4MM algorithm takes place in the kernel. We show that a more elaborate design using two types of digit recoding makes the radix-4 design the best solution for the implementation of this scalable multiplier.

Common subexpression elimination algorithm for low-cost multiplierless implementation of matrix multipliers

The design of multiplierless implementations (which use only adders, subtracters and binary shifts) of fixed-point matrix multipliers is considered and a new common subexpression elimination method is described that recursively extracts signed two-term common subexpressions. Examples are given that show that the resulting adder-cost is significantly lower than for existing algorithms.

Complex constant number serial multipliers

An efficient implementation of a complex number serial multiplier, when the one factor is constant, is presented. The real and imaginary parts of the constant number are represented in canonic signed digit (CSD) form. The corresponding parts of the non-constant factor are represented in two's complement form. The real and imaginary parts of the product are obtained in two's complement form. The CSD representation was chosen because it yields significant hardware reduction. The proposed scheme operates with 100% hardware efficiency; namely, no sign extension words between successive data words are required.

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

In this paper, we present a general approach which specifically targets reduction of redundant computation in common digital-signal processing (DSP) tasks such as filtering and matrix multiplication. We show that such tasks can be expressed as multiplication of vectors by scalars and this allows fast multiplication by sharing computation. Vector scaling operation is decomposed to find the most effective precomputations which yield a fast multiplier implementation. Two decomposition approaches are presented, one based on a greedy decomposition and the other based on fixed-size lookup and this leads to two multiplier architectures for vector-scalar products. Analog simulation of an example multiplier shows a speed advantage by a factor of about 1.85 over a conventional carry save array multiplier. Further simulations using 0.18 /spl mu/ technology show up to 20% speed advantage over Booth encoded Wallace tree multipliers.

A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 μm bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.

A novel three‐dimensional contact finite element based on smooth pressure interpolations

This article proposes a new three-dimensional contact finite element which employs continuous and weakly coupled pressure interpolations on each of the interacting boundaries. The resulting formulation circumvents the geometric bias of one-pass methods, as well as the surface locking of traditional two-pass node-on-surface methods. A Lagrange multiplier implementation of the proposed element is validated for frictionless quasi-static contact by a series of numerical simulations. Published in 2001 by John Wiley & Sons, Ltd.

A novel three‐dimensional contact finite element based on smooth pressure interpolations

AbstractThis article proposes a new three‐dimensional contact finite element which employs continuous and weakly coupled pressure interpolations on each of the interacting boundaries. The resulting formulation circumvents the geometric bias of one‐pass methods, as well as the surface locking of traditional two‐pass node‐on‐surface methods. A Lagrange multiplier implementation of the proposed element is validated for frictionless quasi‐static contact by a series of numerical simulations. Published in 2001 by John Wiley &amp; Sons, Ltd.

Multimedia Execution Hardware Accelerator

In this paper we show that some expressions frequently used in multimedia applications can be formulated as a general add-multiply-add operation. We further show a hardwired implementation of the Add-Multiply-Add instruction which is no more complex than the multiplier implementation. Furthermore we show that two frequently motion estimation operations, the Sum and Mean of Absolute Differences, can be implemented in hardware requiring also approximately the same cycle time as the multiplication. We also show that our approach can be extended easily to provide the computation of the Sum and Mean of Absolute Difference of a 16×16 pixel block in no more than four machine cycles. Additionally we propose a codec hardwired mechanism for the Paeth predictor used in the Portable Network Standard (PNG) that requires at most two general purpose ALU cycles. We extend the paeth unit to include the median, maximum and minimum operations on three inputs with no additional cycle time and we also extend the Add-Multiply-Add unit to include the mean of three numbers. Finally we propose a multimedia hardware accelerator to accommodate all the proposed operations. The proposed unit is an extension of the multiply pipeline with ALU extensions with no extra stages added. The unit operates on 32 instructions in total.