Abstract
With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design
Highlights
Growing of battery-operated multimedia devices requires energy-efficient circuits, digital multipliers which are building blocks of digital signal processors
In that variable precision gating, current input precision information is provided through gating signals from precision detection circuit. These signals are combined with system clock to generate sub-clocks, which are connected to the corresponding registers in pipeline gating with fixed latency for reduced power consumption in pipelined digital systems
Physical constraints file: A Physical Constraints File (PCF) is a text file containing two separate sections: a section for those physical constraints created by the mapper and a section for physical constraints entered by the user
Summary
Growing of battery-operated multimedia devices requires energy-efficient circuits, digital multipliers which are building blocks of digital signal processors. In that variable precision gating, current input precision information is provided through gating signals from precision detection circuit These signals are combined with system clock to generate sub-clocks, which are connected to the corresponding registers in pipeline gating with fixed latency for reduced power consumption in pipelined digital systems. The system clock is distributed to the The additional area cost to implement this technique to different sections as a sub clock based on the precision design pipeline gating multiplier is very little and the of the input data. Based on the discussion above, a set of 8-bit performing 0001×0001, only S0 has useful value This variable precision pipeline multiplier were designed value is selected from the stage right after the AND (Fig. 4). Data directly translates to the number of quantization
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