Synthesis of Modular Multipliers

Abstract

The results of experiments on the circuit implementation of modular multipliers in the design library of ASIC (Application-Specific Integrated Circuits) and FPGA (Field-Programmable Gate Array) are presented. The initial descriptions of modular multiplier projects were given by systems of not fully defined (partial) Boolean functions and algorithmic VHDL descriptions. Logical optimization was carried out in the class of disjunctive normal forms (DNF) and representations of Boolean function systems by BDD (Binary Decision Diagrams). The synthesized circuits were evaluated by area and time delay. It is established that the use of partial Boolean function models and preliminary logi­cal BDD optimization allows one to improve the parameters of synthesized ASIC and FPGA blocks for small module values, however, the best solutions for large module values can be obtained using algorithmic VHDL descriptions of modular multipliers. In the synthesis of modular multiplier circuits as part of an FPGA and the use of ISE and Vivado design systems it is advisable to use synthesized VHDL operations (a*b) mod p.