Multiple Domain Logic Synthesis

Abstract

Field programmable gate arrays (FPGA) and other complex programmable devices (CPLD) require new logic minimization techniques since the cost functions used for conventional target implementations are no longer valid. Until now, existing tools are only adapted to the new requirements. However, the underlying approaches for logic minimization and technology mapping remained the same. We present logic minimization techniques that extend classical approaches. Basic function properties as e.g. linearity, monotony, and symmetry of its variables are detected. They are used in decomposition and partial collapsing steps to group variables with common properties within a multi-level Boolean network. The Boolean functions are stored as decision diagrams. Three different Boolean normal forms are used: disjunctive normal form, Reed-Muller expansion, and equivalence polynomial. Therefore, three types of decision diagrams are needed: binary decision diagrams (BDD), functional decision diagrams (FDD), and equivalence decision diagrams (EDD). A multiple domain minimization approach based on decomposition, domain selection, variable ordering, and variable polarity optimization is introduced.