Multiplier Circuit Research Articles

RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA

Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained reconfigurable cipher logic array to support more cryptographic algorithms; however, it will introduce low flexibility and high overhead, resulting in reduced performance of the coarse-grained reconfigurable cipher logic array. In this article, a high-flexibility and low-cost reconfigurable Galois field multiplication unit (RGMU) is proposed to balance the tradeoffs between the function, delay, and area. All the finite field multiplication operations, including maximum distance separable matrix multiplication, parallel update of Fibonacci linear feedback shift register, parallel update of Galois linear feedback shift register, and composite field multiplication, are analyzed and two basic operation components are abstracted. Further, a reconfigurable finite field multiplication computational model is established to demonstrate the efficacy of reconfigurable units and guide the design of RGMU with high performance. Finally, the overall architecture of RGMU and two multiplication circuits are introduced. Experimental results show that the RGMU can not only reduce the hardware overhead and power consumption but also has the unique advantage of satisfying all the finite field multiplication operations in symmetric cryptography algorithms.

Effective prime factorization via quantum annealing by modular locally-structured embedding

This paper investigates novel techniques to solve prime factorization by quantum annealing (QA). First, we present a very-compact modular encoding of a multiplier circuit into the architecture of current D-Wave QA devices. The key contribution is a compact encoding of a controlled full-adder into an 8-qubit module in the Pegasus topology, which we synthesized using Optimization Modulo Theories. This allows us to encode up to a 21 × 12-bit multiplier (and a 22 × 8-bit one) into the Pegasus 5760-qubit topology of current annealers. To the best of our knowledge, these are the largest factorization problems ever encoded into a quantum annealer. Second, we investigated the problem of actually solving encoded PF problems by running an extensive experimental evaluation on a D-Wave Advantage 4.1 quantum annealer. In the experiments we introduced different approaches to initialize the multiplier qubits and adopted several performance enhancement techniques. Overall, 8,219,999 = 32,749 × 251 was the highest prime product we were able to factorize within the limits of our QPU resources. To the best of our knowledge, this is the largest number which was ever factorized by means of a quantum annealer; also, this is the largest number which was ever factorized by means of any quantum device without relying on external search or preprocessing procedures run on classical computers.

A new ultra-low power wide tunable capacitance multiplier circuit in subthreshold region for biomedical applications

Implementing large capacitors in integrated circuits demands an occupation of a relatively significant large silicon area on-chip, which strictly limits the capability of the physical implementation of low-frequency integrated circuits that mostly require high capacitance values to provide large time-constants. Capacitance multipliers have been proposed to overcome this issue to realize high-value active capacitances in a small chip area. This paper proposes a new current-mode ultra-low power capacitance multiplier based on the floating capacitance Super Flipped Current Follower (SFCF) circuit which employs two AB class cascaded stages. The main novel idea behind the proposed circuit is combining the cross-coupling Quasi-Floating Gate (QFG) with the class-AB techniques and employing the Super Flipped Current Follower (SFCF) circuit, to enhance the adjustment efficiency ratio (M) factor, while also achieving a high scaling factor “K”. As a result, the proposed circuit achieves higher K value at the lower power and chip size area costs, while providing better adjustment efficiency ratio (M), which realizes a better “capacitance adjustability-power” trade-off. The proposed circuit provides other advantages such as: wide electronic tunability of scaling factor K, large Parallel Load Resistance (PLR) value, small value of Equivalent Series Resistance (ESR), relatively small chip size area, and a high ratio of adjustment efficiency (M). The total power consumption of the proposed circuit is obtained as 101 nW, using a base capacitance (Cb) of 1 pF, which leads to the realization of a maximum achievable equivalent capacitance (Ceq) of 1604 pF. In addition, the performance of the proposed tunable capacitance multiplier is examined in the realization of a wide-tunable low-pass filter structure. Furthermore, the performance robustness of the proposed circuit is investigated by the Monte-Carlo and PVT analyses in different technology corners, which justify the good performance of the proposed circuit that makes it a proper candidate to be used in ultra-low power biomedical signal processing.

Implementation of Non-Isolated High Gain Interleaved DC-DC Converter for Fuel Cell Electric Vehicle Using ANN-Based MPPT Controller

A high conversion ratio DC-DC converter is crucial for fuel cell electric vehicles (FCEV). A fuel cell-based non-isolated high gain integrated DC-DC converter for electric vehicles is proposed in this paper. The system comprises an interleaved boost converter (IBC) at the source end, a switched capacitor cell, coupled inductors, a passive clamp circuit, and a voltage multiplier circuit (VMC). Its significance is to achieve the voltage conversion gain of 12.33 at a conversion ratio of 0.45. The idea is to use a proton exchange membrane fuel cell to power electric vehicles through a high-gain DC-DC converter. The use of an ineffective MPPT can result in lower energy conversion efficiency. Thus, this system incorporates a maximum power point tracking (MPPT) controller based on a neural network, which relies on the radial basis function network (RBFN) algorithm to track the maximum power point of the PEMFC accurately. The comparative study of the fuel cell electric vehicle (FCEV) structure with the RBFN-based MPPT technique was evaluated with that of the fuzzy logic technique using the MATLAB/Simulink platform (R2021b (MATLAB 9.11)). A 1.5 kW experimental prototype is designed with a switching frequency of 10 kHz to validate the design analysis, and its pursuance is compared between RBFN and FLC-based controllers. This manuscript will be a significant contribution towards evidencing a sustainable environment.

An efficient quantum circuit implementation of Shor’s algorithm for GPU accelerated simulation

In this study, we introduce a novel implementation of Shor’s algorithm specifically designed for the Graphics Processing Unit (GPU) acceleration framework. Our focus lies on achieving efficient execution of the modular multiplication circuit through GPU simulation. To seamlessly integrate our design into the PyQPanda library framework, we made necessary modifications, making a deliberate trade-off by sacrificing a small number of quantum resources to leverage the advantages of GPU acceleration. Subsequently, we conducted simulations and rigorously validated the functionality of our circuit using the PyQPanda library, resulting in a significant speedup compared to a central processing unit-only mode.

Quantum Circuit Optimization of Arithmetic Circuits using ZX Calculus

Quantum computing is an emerging technology in which quantum mechanical properties are suitably utilized to perform certain compute-intensive operations faster than classical computers. Quantum algorithms are designed as a combination of quantum circuits that each require a large number of quantum gates, which is a challenge considering the limited number of qubit resources available in quantum computing systems. Our work proposes a technique to optimize quantum arithmetic algorithms by reducing the hardware resources and the number of qubits based on ZX calculus. We have utilized ZX calculus rewrite rules for the optimization of fault-tolerant quantum multiplier circuits where we are able to achieve a significant reduction in the number of ancilla bits and T-gates as compared to the originally required numbers to achieve fault-tolerance. Our work is the first step in the series of arithmetic circuit optimization using graphicalrewrite tools and it pavesthe way for advancing the optimization of various complex quantum circuits and establishing the potential for new applications of the same.

Single inductor multi-PZTs SECE and electromagnetic voltage multiplier rectifier hybrid interface circuit

This paper proposes a single inductor multi-piezoelectric transducers (PZTs) SECE and electromagnetic voltage multiplier rectifier hybrid interface circuit (MP-SECE-VMR), which harvest energy from multi-input PZTs and electromagnetic generator (EMG). The MP-SECE-VMR adopts a voltage multiplier rectifier circuit, utilizing the diode-connected MOSFET configuration which used as diodes to effectively reduce voltage losses during rectification. Experimental tests confirm that this circuit efficiently extracts energy from PZTs despite differences in their phase relationships. The low input voltage from the EMG is effectively elevated through the voltage multiplier rectifier, enabling simultaneous extraction with the PZTs. The proposed MP-SECE-VMR circuit extracts 1.2 mW of power from two PZTs with open-circuit amplitudes of 9 V and 11 V respectively, as well as from an EMG input with an open-circuit amplitude of 3 V and a frequency of 5 Hz. Furthermore, the proposed circuit effectively enhances output power while expanding the working load range compared to single-source energy extraction.

An efficient high-gain bidirectional interleaved boost converter for PV integration to DC microgrid.

The design of a power electronic interface for high voltage difference DC buses is a key aspect in DC microgrid applications. A multi-port non isolated interleaved high-voltage gain bidirectional converter, which facilitates bidirectional power transfer and islanded operation in a DC microgrid, is presented in this paper. The forward high-voltage transfer ratio is achieved using a voltage multiplier circuit, and the high-gain step-down power conversion is performed using a resonant power module. A novel power transfer selection algorithm is proposed to control power flow among the interfaces of the RES, ESS, and DC grid converters, which utilizes the net power difference as the basis for switching the converter. The proposed converter is simulated for a 24 V PV source, 12 V battery, and 400 V DC grid interface using MATLAB/SIMULINK. A 200 W hardware prototype is implemented. The simulation results for voltages, currents, and power flow among RES, ESS, and microgrid DC bus proved an excellent voltage regulation, efficient power conversion, and a feasible duty cycle range with high voltage gain. These observations are validated through equivalent experimental results. A comparison is made regarding achieved gain, component sizing, achievable power transfer modes, efficiency, and control complexity with existing converters for DC microgrid applications. The presented topology proved to be a better interface with multiple-mode support with high efficiency.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

A new soft‐switching high gain DC/DC converter with bipolar outputs

AbstractThis paper introduces a new single‐input multi‐output step‐up DC/DC converter with soft‐switching performance and low input current for renewable energy applications. The proposed topology uses a three‐winding coupled‐inductor (TWCI) and voltage multiplier circuits to achieve high voltage gains. The bipolar output voltages of the proposed converter can be varied independently by tuning the turns ratios of the TWCI. Due to the semi‐trans‐inverse specification of the suggested topology, high voltage gains can be obtained under a lower number of turns ratio in the magnetic device. Furthermore, a regenerative passive clamp technique mitigates the voltage stress on the single power switch. Additionally, the power dissipations are further reduced by considering a resonant tank in the circuit. In the converter, the parasitic leakage inductances of the TWCI windings help to provide the soft‐switching conditions for the switch and also to eliminate the reverse‐recovery loss for all converter diodes. The operating mode of the presented converter has been introduced and the steady state, along with the main operating equations have also been derived. Finally, the theoretical analysis is verified by a sample prototype 235 W at the input voltage 25 V and outputs of 200 V and −200 V.

Quantum Circuit Design for Integer Multiplication Based on Schönhage–Strassen Algorithm

Quantum arithmetic circuits has attracted extensive attention recently since it plays fundamental roles in many applications of quantum computing. Specifically, quantum circuits for integer multiplication are of great significance to various quantum algorithms including Shor’s integer factorization and discrete logarithm algorithm. In this paper, we design a family of quantum circuits for integer multiplication based on the famous classical integer multiplication algorithm, Schönhage-Strassen algorithm. We have made slight modifications to the algorithm to simplify its quantum circuit implementation. As a result, the quantum circuit we designed has gate depth O(log2n). To the best of our knowledge, this is the first poly-logarithmic depth quantum circuit for integer multiplication which keeps the circuit size and the number of ancillary qubits sub-quadratic. Our design has size O(nlognloglogn) counted by elementary quantum gates which is the same as the time complexity of Schönhage-Strassen algorithm, and it consumes O(nlognloglogn) clean ancillary qubits. In addition, we also utilize a weaker version of Schönhage-Strassen algorithm to give a family of circuits which has depth at the same order O(log2n) but with significantly smaller constants, while still keeping the size and number of ancillary qubits sub-quadratic.

A 40-Pulse Autotransformer Rectifier Based on New Pulse Multiplication Circuit for Aviation Application

In this paper, a new simple pulse multiplication circuit (SPMC) with low current stress is proposed, in order to upgrade a normal 20-pulse autotransformer rectifier (20PAR) to a 40PAR. The proposed SPMC comprises two tapped inter-phase reactors (TIPRs) and two additional diodes with lower conduction losses. The proposed SPMC does not require a zero-sequence blocking transformer (ZSBT) compared to conventional pulse multiplication circuits, which leads to simplicity in implementation. Simulation and experimental results show that the total harmonic distortion (THD) of the input current using 40PAR is less than 3%, which meets the DO-160G requirements for aviation applications.

Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA

Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

Floating parallel lossy inductance, parallel lossy capacitance, parallel C‐D, and lossless capacitance multiplier circuits using current feedback operational amplifiers

SummaryA new synthetic floating simulator topology is proposed which realizes lossy parallel inductance (R‐L), lossy parallel capacitance (R‐C), lossy parallel C‐D, and lossless floating capacitance multiplier (FCM) circuits using only three current feedback operational amplifiers (CFOA) as active elements and three impedances. In all the presented circuits, the value of L, C, and D is independently controllable through a single resistance without requiring any matching condition for passive elements. A novel feature of the proposed circuit involves a straightforward adjustment in the CFOA connections, allowing the circuit to function as either a floating lossless immittance simulator or a floating series‐type lossy immittance simulator. Various application examples of the presented circuits such as lead compensator, lag compensator, first‐order high‐pass filter, and fourth‐order Butterworth filter are also given to justify the theoretical analysis. To validate the workability of the proposed circuits, several analyses are conducted, including frequency analysis, transient analysis, Monte‐Carlo analysis, and temperature analysis, using the macro‐model of AD844 in the SPICE simulation tool. Experimental results of the parallel R‐L simulator and application examples are also provided using commercially available IC AD844‐type integrated CFOAs.

A high speed and power efficient multiplier based on counter-based stacking

<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>

CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

Single-electronic Multi-level Adders

Since metal-oxide-semiconductor microelectronic structures have reached small-scale and quantum limitations, technological models of single-electron nanocircuits of multi-level adders have been created in the work. It has been proven that one bit of information can be encoded by the presence or absence of one electron on a quantum island cluster.This paper provides a simulation of a 4×4 multiplier circuit on the proposed one-bit full adder. As a result, a comparison with other adders was made, an analysis of energy dissipation depending on temperature and the dissipated power of the existing and proposed multipliers in nW was carried out. As a result, it was found that the proposed adder has better properties compared to similar ones. As a result of the work, the simulation of the 4×4 multiplier circuit was performed, and the simulation results were obtained. Modeling of the circuit was performed in QCAD DESIGNER software.

Enhancing the Performance of Human Motion Energy Harvesting through Optimal Smoothing Capacity in the Rectifier

Energy harvesting offers a promising solution for powering a growing variety of low-power electronics; however, harnessing energy from human motion, with its irregular and low-frequency bursts of power, presents conversion challenges. As rectification is a common part of it, this study investigates the influence of smoothing capacitor values on rectifier output for short, intermittent signals. We propose an analytical model that identifies an optimal smoothing capacity for the full-bridge rectifier, considering harvester internal resistance, frequency, and load resistance and leading to the highest average output voltage after rectification. The model was validated with detailed computer simulations; furthermore, a similar effect was revealed on a voltage multiplier circuit as well. Experimental measurements demonstrate that deviating from the optimal smoothing capacity results in up to 10% decrease in rectified RMS voltage, leading to significant drops in output power in specific energy harvesting systems. A real-world experiment with a human motion energy harvester further confirmed the findings in a naturally varying generation environment.

An unbalanced ternary multiplier cell based on graphene nanoribbon field-effect transistors for PVT-tolerant low-energy portable applications

The potential benefits of using multiple-valued logic (MVL), especially ternary logic, which includes less interconnections, quicker response times, and smaller chip sizes, has gained the interest of designers of digital systems. A practical solution for achieving circuits with multiple thresholds in an efficient manner is through using graphene nanoribbon field-effect transistors (GNRFETs) that have modifiable threshold voltage values by adjusting the width of graphene nanoribbon. This article leverages the unique characteristics of GNRFETs and proposes a new design for a single-trit ternary multiplier (TMUL) circuit. The proposed TMUL uses two supply voltages to block direct current paths from high-to-low voltage levels, resulting in power and energy savings. Additionally, unary operators such as negative and positive ternary inverters and the complement of decisive literal are used to reduce transistor count and improve circuit performance. To thoroughly evaluate the performance of the proposed GNRFET-based TMUL circuit, extensive simulations are performed using Synopsis HSPICE tool and 32-nm channel length GNRFET devices, while taking into account the influences of process-voltage-temperature variations (PVT). The simulation results confirm the robustness and reliability of the proposed design, exhibiting reductions in power consumption by 71.18% to 76.36%, and energy consumption by 67.78% to 86.54%, when compared to other state-of-the-art TMUL circuits available in literature. Moreover, Monte-Carlo simulations have been performed to demonstrate that the suggested design exhibits reduced sensitivity towards significant process variations. As a result, the presented TMUL design can be a good choice for use in low-energy battery-operated portable multimedia device.

Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators

Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in the analog domain, can further improve this energy advantage. An energy efficient multiply-accumulate cell for all-analog neural layer processing macros is presented. The proposed analog two-quadrant multiplier circuit consists of two complementary MOSFETs where the pulse width modulated input activation is applied to the gates and the weight signal to the isolated back-gate. The analog multi-bit resolution weight is dynamically stored on a memory capacitor. The multiply-accumulate operation result is represented by charge accumulated on a summation line and drawn from or put onto a computation capacitance. Simulation results based on a 22 nm FD-SOI CMOS technology show that the cell consumes about 0.67 fJ for a circuit-level multiply-accumulate operation. An area efficiency of 166 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{12}$</tex-math> </inline-formula> MAC/s/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> is achieved.