Multiplier Circuit Research Articles

Low-Cost High-Voltage Power Supply for Hydraulically Amplified Self-Healing Electrostatic Applications

HASEL (Hydraulically Amplified Self-Healing Electrostatic) actuators have gathered momentum in recent years; they are made of very-low-cost materials, making it easy for anyone to develop their own actuators, and they are “soft” and can achieve tasks that are very difficult to complete with traditional rigid actuators, e.g., grasping soft objects. Unfortunately, HASEL actuators are driven by high-voltage (HV) power supplies, which are expensive to control accurately and difficult to scale up for multichannel applications, e.g., prostheses. This paper presents a low-cost HV power supply designed for HASEL applications that generates 2–10 kV DC at 5% of the cost of the existing HV power supplies used in HASEL actuators. At the core of our design, there is a new control strategy based on controlling the charging and discharging of the actuator from the supply’s low-voltage (LV) side rather than switching the HV side with expensive HV optocouplers. Discharge is achieved via a secondary transformer and multiplier circuit, generating a negative HV output capable of discharging the HASEL effectively and safely up to 10 kV.

Power electronics for green hydrogen generation with focus on methods, topologies, and comparative analysis.

This research article meticulously examines advanced power electronic converters crucial for optimizing electrolyzer perfor- mance in hydrogen production systems. It conducts a thorough review of mature electrolyzer types, detailing their specifications, electric models, manufacturers, and scalability. To meet the high current and stable DC voltage demands of industrial electrolyzers, the study delves into a broad spectrum of AC-DC and DC-DC converter topologies. It explores cutting-edge solutions like 12-pulse and 20-pulse rectifiers, advanced higher multi-pulse rectifiers utilizing conventional and auto-connected transformer units, Multi-Step Auto-connected Transformers (MSAT), polygon autotransformers, and auxiliary filters and circuits such as pulse multiplication circuits and active power filters. These innovations significantly reduce harmonic distortions and enhance power quality, addressing challenges inherent in conventional 6-pulse diode bridge rectifiers. The research also focuses on the efficiency and power factor correction capabilities of Active Front End (AFE) converters and the 3L-DNPC rectifier. Additionally, it investigates various DC-DC converters, including the Continuous Input Current Non-Isolated Bidirec- tional Interleaved Buck-Boost DC-DC Converter, the Interleaved Buck Converter (IBC) with extended duty cycles, the 3-level buck-boost converter with a coupled inductor, Quadratic converters designed for fault tolerance, the three-level interleaved buck converter, among others. Converter designs like the galvanically isolated half-bridge converter with controlled reverse-blocking switches for achieving zero voltage switching (ZVS), the Push-Pull isolated DC-DC converter prioritizing current stability, and the Isolated Full-Bridge Boost Converter (IFBBC) adept at handling fluctuating power outputs from renewable sources are also explored. Moreover, the study scrutinizes a range of converter configurations such as the Two-stage ZVT boost converter with LCL-Type SRC, multiphase interleaved DC-DC stage, and three-port isolated DC/DC converter for efficient integration with multiple energy sources concurrently. Discussing feature trends in power-to-hydrogen systems, the research reviews multi-cell modular rectifiers and multi-stage rectifiers. Overall, the study underscores the critical role of advanced converter topologies in enhancing efficiency, reliability, and power quality in electrolyzer systems, thereby contributing significantly to the progression of sustainable energy technologies.

An Improved Series 36-Pulse Rectifier Based on Dual Passive Pulse-Doubling Circuit on the System DC Side

The series-type 12-pulse rectifier generates a large amount of harmonics in the AC side current due to the strong nonlinearity of its rectifying diodes, causing serious harmonic pollution to the power grid. This article proposes a series 36-pulse rectifier based on a DC side dual passive frequency-doubling circuit to suppress the AC side current harmonics of a 12-pulse rectifier. The rectifier uses two symmetrical passive pulse multiplication circuits to regulate the circulation in the DC side circuit, increasing the output voltage and current state of the rectifier bridge, thereby increasing the number of pulses in the rectifier from 12 times to 36 times. Firstly, the working principle of the rectifier and the working mode of the dual passive frequency-doubling circuit were analyzed. Secondly, the harmonic suppression mechanism of the rectifier input current was revealed, and the frequency-doubling characteristics of the load voltage were analyzed. Finally, the correctness of the theoretical analysis was verified through a semi-physical platform. The verification and comparison results show that under the optimal conditions of the injecting transformer turns ratio, the DPPC can not only reduce the THD value of the input current by about 1/3 (from 14.87% to 4.78%) but can also increase the fluctuation frequency of the load voltage by 3 times (from 12 to 36), while improving the power quality of the AC/DC side rectifier and achieving the low harmonic operation of the rectifier. The proposed 36-pulse rectifier can effectively suppress harmonics; it has the advantages of simple structure, strong robustness, and high output voltage gain, and it is suitable for medium-voltage and high-voltage high-power rectification applications.

Construction of small size and high output triboelectric nanogenerator by multi-layer-stacking and charge excitation

Abstract The triboelectric nanogenerator (TENG) has been considered a low-frequency mechanical energy collection and conversion device in the modern era. The reasonable stack structure of TENG is an effective method to boost its electric output performance within a limited space. Nevertheless, relying solely on the stacking structure, the TENG is unable to produce excessive output due to the low contact electrification capability of its materials. Hence, there are still significant challenges in enhancing the output performance of stacked TENGs. We propose a multi-layer-stack TENG (M-TENG) with two zigzag-shaped (Z-shaped) multilayer units interleaving and stacking with each other, which enormously enlarges the effective utilization area. Furthermore, a voltage multiplier circuit (VMC) incorporating a Zener diode allows the transfer charge to approach the critical threshold and maintain a stable output. The transfer charge and current of M-TENG integrated with a VMC can reach 1.52 μC and 86 μA, respectively, with the maximum output of the TENG being 8.65 mW (5 MΩ). To prove it as a self-power device, M-TENG excited by a VMC is employed to power 912 light-emitting diodes (LEDs) and three temperature and humidity sensors with a power management circuit (PMC), respectively. This work offers a new method for optimizing stacking-layer TENG electric output performance in a narrow space.

Adaptive prairie dog optimization based variable length conditional counter for designing multiplier

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.

Grounded and floating memristor emulator employing ICCTA: decremental or incremental operation

ABSTRACT This article describes floating and grounded memristor emulator built with an Inverting Current Conveyor Transconductance Amplifier (ICCTA). One ICCTA, one capacitor, and three resistors are used to implement the charge controlled floating memristor emulator. In contrast, a flux controlled grounded memristor emulator consists of one ICCTA, one resistor, and one capacitor. Both presented circuits do not incorporate complex circuits such as analog multiplier circuits, passive inductors, and analog to digital converter circuits in their implementation, which is advantageous in terms of circuit realisation. The designed circuits may be operated in incremental as well as decremental configurations by appropriate setting of MOS switches. In addition, PVT (process, voltage, and temperature) analysis of the proposed memristor is also included. Furthermore, the non-ideal explanation of the proposed circuits is mathematically examined. The proposed emulators are simulated in SPICE simulator using 180 nm technology. Meminductor circuit and memristor-based low pass filter are used to validate the effectiveness of the designed circuits.

Energy efficient Wallace multiplier using symmetric stacking counter circuit

Multipliers show a dynamic part in numerous uses such as digital signal processing, filters and so on. Hence, the performance of the multiplier circuit has also to be improved more for better results. The circuit of the multiplier should be more compact and efficient to achieve the best outcome. Symmetric stacking counter circuit is designed using reversible logic gates and it reduces the power consumption. Various symmetric stacked counters are designed and used to implement the Wallace tree multiplier. The proposed multiplier is consumes 0.798mw of power and PDP of 2.47. The designed multiplier is power efficient as compared with existing methods with slight increase in delay. The proposed multiplier is used in low power application like modulators and demodulators.

Area-energy optimized ternary multiplier usingefficient design approaches in GNRFET technology

The semiconductor industry has long benefited from CMOS transistors in realizing advanced VLSI circuits. However, achieving area-energy optimization in CMOS-based VLSI circuits has become increasingly challenging due to short-channel effects. Another obstacle in manufacturing these transistors is the adoption of body-biasing techniques to adjust the threshold voltage (Vth) for developing ternary logic-based circuits. Researchers are now exploring emerging devices like graphene nanoribbon field-effect transistors (GNRFET) as potential candidates for future electronics. GNRFET devices not only leverage graphene’s remarkable properties but also benefit from the ability to achieve distinct Vth through tuning the width of graphene nanoribbons. This paper focuses on using tri-state 32-nm GNRFET devices to implement a novel area-energy optimized ternary multiplier circuit. To attain a logic ‘1′ in the proposed circuit, a power-efficient voltage division technique is employed. Additionally, efficient design approaches are used to reduce the critical path length and decrease the number of necessary transistors. Simulation results using HSPICE demonstrate that the proposed design reduces energy consumption by a minimum of 6.75% and up to 37.50% compared to other state-of-the-art 32-nm GNRFET-based TMUL circuits. Furthermore, the proposed design decreases both the area and complexity by utilizing a single-VDD and incorporating 24 transistors.

Low Power and Delay Efficient 4x4 Array Multiplier Using 20T Hybrid Adder in 90nm Technology

In this paper, the 4x4 array multiplier was designed and its power Delay Product (PDP) was analyzed. An array of full adders and half adders is used in an array multiplier, a combinational circuit, to multiply two binary values. The total power consumed by the array multiplier can be minimized by introducing a hybrid adder which constitutes 20T. In the 20T hybrid adder maximum power consumption is mostly dependent on the performance of the 10T XOR-XNOR circuit. As a result, it offers both full swing output and good capabilities without the need for an external inverter. Therefore, the array multiplier was designed by a hybrid adder instead of a conventional adder circuit to achieve low power and delay efficient multiplier circuit. The hybrid adder circuit outperforms its counterparts showing that PDP reduces 18% more than available conventional full adders. Using 90nm CMOS technology, the suggested circuits' performance is evaluated by stimulating them in a cadence virtuoso environment.

A two stage pipeline architecture for hardware implementation of multi-level decomposition of 1-D framelet transform

In this paper a two stage pipeline architecture for computation of multilevel decomposition of framelet transform is proposed. To handle the problem of perfect reconstruction, an area efficient symmetric extension router is used that duplicates the appropriate number of data samples of input signal at the boundary followed by reflection about the symmetry axis. In addition, to reduce the period and number of clock cycles required for computing the framelet transform, the inter-stage and intrastage pipeline of the computational units is maximized. The inter-stage pipelining is obtained by distributing the various levels of decomposition among the computational units of two stages, and a synchronization mechanism is adopted to reduce the total number of clock cycles. Similarly, the intrastage pipelining is achieved by using the pipeline registers such that the clock period is limited to the delay of multiplier and accumulator (MAC) circuit of the finite-impulse response (FIR) filter. To validate the feasibility and functionality of the proposed hardware architecture, the design is implemented on Artix7 XC7A100TCSG324-1 field-programmable gate array (FPGA) for the case of framelet transform with one low-pass and two high-pass filters. The proposed architecture is able to operate at a maximum clock frequency of 112 MHz.

Design and Simulation of Vedic Multiplier Using Verilog HDL

Abstract: This Paper is created for the simulation of a high speed Vedic multiplier. In the proposed paper, the multiplier circuit is designed by using algorithms that involve Vedic Mathematics. Calculations that involve Vedic mathematics are derived from the old contexts known as Vedas. The VHDL programs are synthesized and simulated using Xilinx ISE simulator. The study of Vedic multipliers is done in comparison with the conventional multipliers to find the fact that which multiplier is fast and efficient and the research and analysis has shown that the Vedic multiplier is more efficient than conventional multipliers because of its fast response in digital signal processing and it gives less delay in system logic design. Vedic mathematics used in the Vedic multiplier increases the speed of multiplier as it reduces the number of partial products. Hence, the speed of the overall digital design can be increased by implementing a Vedic multiplier.

Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder

Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder

RF-DC conversion for RF energy harvesting from digital TV signals using voltage multiplier circuits

RF-DC conversion for RF energy harvesting from digital TV signals using voltage multiplier circuits

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS

Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid of the PPA design, an assessment of adders’ availability for low power VLSI designs with minimal propagation delay is conducted. Using these performance measures, this study compares and evaluates the performance of several parallel prefix adders, allowing readers to select the optimum adder architecture for their application Specific Integrated Circuits implementations. The three adder topologies taken into considered in this Article include the Han carlson adder, Brent kung, Kogge stone adders. Xilinx ZYNQ XC7Z020 (7000 series) SoC is used to implement the adders using the Vivado Design Suite 2014 and Verilog.

Review of Cockcroft-Walton High Voltage Low Current DC Power Supplies

High-voltage power supplies are key for developing particle accelerators, neutron generators, x-ray systems, ion implantation, etc. This paper reviews various developed voltage low current power supplies based on Cockcroft-Walton voltage multiplier circuits for accelerator-based neutron sources and other industrial and medical applications. The paper presents a detailed review of the topology of the power supply used for the high voltage generation, the key design parameters, key active and passive components used in the High Voltage (HV) system, key experimental results, protection and measurement circuit used in the power supply and about the system performance. The improvement that occurred in the size and performance of the power supplies due to the development in the technology of the magnetic components, semiconductors and energy storage devices in successive years is apparent in the discussion. Finally challenges and possible solutions for the compact design and system performance are concluded for the development of high voltage low current power supplies.

Designs of the divider and special multiplier optimizing T and CNOT gates

Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. But neglecting the cost of CNOT gates may lead to a significant underestimation. Moreover, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. As a result, reducing T-count, T-depth, CNOT-count, CNOT-depth, and circuit width has become the important optimization goal. We use 3-bit Hermitian gates to design basic arithmetic operations. Then, we present a special multiplier and a divider using basic arithmetic operations, where ‘special’ means that one of the two operands of multiplication is non-zero. Next, we use new rules to optimize the Clifford + T circuits of the special multiplier and divider in terms of T-count, T-depth, CNOT-count, CNOT-depth, and circuit width. Comparative analysis shows that the proposed multiplier and divider have lower T-count, T-depth, CNOT-count, and CNOT-depth than the current works. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the best current work. Further, the circuit widths of the proposed n-bit multiplier and divider are 3n. I.e., our multiplier and divider reach the minimum width of multipliers and dividers, keeping an operand unchanged.

A 0.6 V voltage reference circuit with 57 ppm/°C temperature coefficient, 73 KΩ output impedance and 0.080%/V line sensitivity for energy efficient applications

In this paper, a voltage reference circuit generating 0.6 V developed in the Semiconductor Laboratory (SCL) 0.18 μm standard CMOS technology has been presented. It is based on the principle of Beta multiplier circuit. Operating under a supply voltage of 1.8V, the proposed reference accomplishes a line sensitivity as low as 0.080%/V across a voltage range of 1.8 V to 3.5 V. In addition to a low line sensitivity, it achieves a low temperature coefficient of 57 ppm/ °C over the temperature range of −40 °C to +85 °C. The circuit furnishes a power supply rejection ratio (PSRR) of −75.72 dB. The improved load regulation feature allows the circuit to drive loads as low as 73 KΩ with minimum variation. A reliable nature of the circuit has been observed on examining the response for different process corners and variations.

Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC

In order to compensate for the non-linearity of an electronic device, an exponentiation conversion circuit that can change the power exponent to any value has been proposed. The exponentiation conversion circuit multiplies the logarithmically converted input signal by a power exponent value to perform exponential conversion. As a result, we can obtain the power function characteristic of a power exponent value. This circuit is a small-scale circuit that utilizes the exponential characteristics of the MOSFET subthreshold region. In a conventional circuit, expansion of the signal dynamic range and reduction of the power supply voltage have been an issue. In this paper, it was confirmed by simulation that the signal dynamic range has expanded by optimizing the current density of MOSFETs. In addition, the linearity of the multiplying circuit was improved by feedback produced by the operational amplifier circuits. We proposed reducing its power supply voltage from 6.0 to 3.3 V by a new multiplying circuit that can eliminate the restriction of maximum voltage gain. Our circuit expands its signal dynamic range from 17.5 to 42.7 dB in condition of the power exponent value from 0.50 to 2.0.

Logic cloning based approximate signed multiplication circuits for FPGA

As hardware circuits become larger and more intricate, there is a growing need for approximate circuit techniques. These approaches offer a trade-off, sacrificing some system accuracy in exchange for greater hardware resource efficiency and energy conservation. In the context of FPGA-based computation-intensive arithmetic multiplication, Logic Cloning (LC) is introduced to systematically induce controlled approximation. LC-Baugh Wooley (BW) circuits deliver exceptional error performance with precise approximation, while LC-Booth circuits are characterized by reduced Look-Up Table (LUT) resource consumption. In the case of 16-bit operands, LC methods effectively reduce LUT resource consumption by 31.05% for Booth and 36.85% for BW. Additionally, compared to their accurate counterparts, they lower the Power Delay Product (PDP) by 34% for Booth and 35% for BW. When it comes to symbol error-rate performance for Zero Forcing (ZF) Multiple Input Multiple Output (MIMO) uplink detection, these LC approximate multiplication circuits exhibit robust performance, particularly LC-BW circuits, which closely match the accuracy of ZF detection, followed by LC-Booth circuits.