Multiple Stuck-at Faults Research Articles

Detection and identification of input/output stuck-at and bridging faults in combinational and sequential VLSI networks by universal tests

In this paper we present universal tests for detection or identification of single and multiple stuck-at and bridging faults in combinational and sequential VLSI networks. Denote by P(T, F, m, k, s) the fraction of all devices with m inputs, k outputs and S feedback lines such that all faults from a set F of possible faults are detected (respectively, identified) by test T. We say that T is a universal test detecting (identifying) all faults from F if lim m → ∞ P(T, F, m, k, s) = 1. In this paper we consider single and multiple stuck-at and bridging faults at input or output lines. For these faults we construct corresponding universal tests T, estimate probabilities P(T, F, m, k, s) of fault detection or identification and present lower and upper bounds for the minimum number N(m, k, s) of test patterns in universal tests. Asymptotic optimality of the suggested universal tests is proved for the important case of single stuck-at and bridging faults. We also present practical examples of devices and tests which illustrate the usefulness of the estimates of minimum numbers N(m, k, s) of test patterns. For the universal tests T proposed in this paper probabilities P(T, F, m, k, s) of fault detection or identification converge to one very fast. This implies that these universal tests may be quite efficient either as a first step in a testing procedure or in the case when a broad spectrum of complex VLSI devices has to be tested.

A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms

Poage has constructed a complex fault detection algorithm which generates a complete and minimal test set of all multiple stuck-at faults of a given combinational network. Several authors have derived from his method fast and simple multiple fault detection algorithms, which are claimed to generate complete test sets with a near-minimal or near-optimal number of tests. We show that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of tests is sufficient for a complete multiple fault detection test set.

On Necessary and Sufficient Conditions for Multiple Fault Undetectability

This correspondence states necessary and sufficient conditions for a multiple stuck-at fault in a combinational network to be undetected by a test set. The conditions are given in terms of fault masking relationships. It is shown that several other statements on this subject which have appeared in the literature are invalid.

On the Design of Easily Testable Iterative Systems of Combinational Cells

A design procedure is shown which allows the construction of one-dimensional iterative systems of combinational cells with good single stuck-at fault test complexity. Let S be a system where one of the M input words and two of the N states are defined for test purposes and the cells are realized as AND–EXOR normal form circuits, then S is testable with at most [log <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (M x N) + 6] tests for all single faults and for any number of cells. A weaker restriction is shown, where no normal form realization is necessary, and which gives good testability for single or multiple stuck-at faults of the input/output and interconnection lines of cells.

Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"

An efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM's) for any decoder implementation is presented. Another algorithm which does not assume any particular wired logic behavior of simultaneously accessed storage locations, is also presented.

A Note on Testing Logic Circuits by Transition Counting

Test sets to detect single and multiple stuck-at faults in combinational networks by transition counting are given.

Multiple Fault Detection for Combinational Logic Circuits

An algorithm for generating test sets to detect all the multiple stuck-at-faults in combinational logic circuits is presented. This algorithm generates a test set using a set of functions, called representative functions, which consists of much fewer functions than all possible multiple stuck-at fault functions, but is sufficient for test generation. Two different methods of finding such a set of representative functions are presented. The test sets derived from the set of representative functions obtained by the first method will be smaller than that by the second method, but the second method is much simpler than the first especially for highly redundant circuits. Nevertheless, the complexity of this algorithm using the first method is about the same as that of Bossen and Hong's algorithm which is the simplest existing algorithm under the multiple stuck-at fault assumption, and yet the number of tests in a test set generated will always be smaller for redundant circuits and the same for irredundant circuits as that generated by Bossen and Hong's algorithm for irredundant circuits.

An Examination of Algebraic Test Generation Methods for Multiple Faults

A generalized test function (GTF) is derived that gives all tests for a multiple stuck-at fault in a combinational logic circuit. The GTF is then used as the basis for an examination of several algebraic test generation methods that have appeared in the literature. Deficiencies are found in some methods.