Multiple Stuck-at Faults Research Articles

Bilateral Testing of Nano-scale Fault-Tolerant Circuits

As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS'85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.

Fault Detection Architectures for Field Multiplication Using Polynomial Bases

In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field

Combinational automatic test pattern generation for acyclic sequential circuits

It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for the most general class of acyclic sequential circuits. Without inserting any real hardware, we create a functionally equivalent balanced ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs and gates are duplicated in this model, which is converted into a combinational circuit by shorting all flip-flops. A test vector obtained by a combinational ATPG program for a fault in this combinational circuit is transformed into a test sequence to detect a corresponding fault in the original sequential circuit. A combinational ATPG program finds tests for all but a small set of faults that must be explicitly detected as multiple-faults. Those are modeled for ATPG using the second contribution of this work, which is a generalized method to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most n+3 modeling gates for a fault of multiplicity n. We show that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. Benchmark results show at least an order of magnitude saving in the ATPG CPU time by the new combinational method over sequential ATPG.

Incremental fault diagnosis

Fault diagnosis is important in improving the circuit-design process and the manufacturing yield. Diagnosis of today's complex defects is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations and fault models. To tackle this complexity, an incremental diagnosis method is proposed. This method captures faulty lines one at a time using the novel linear-time single-fault diagnosis algorithms. To capture complex fault effects, a model-free incremental diagnosis algorithm is outlined, which alleviates the need for an explicit fault model. To demonstrate the applicability of the proposed method, experiments on multiple stuck-at faults, open-interconnects and bridging faults are performed. Extensive results on combinational and full-scan sequential benchmark circuits confirm its resolution and performance.

A new classification of path-delay fault testability in terms of stuck-at faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.

Fault Testing for Reversible Circuits

Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test-set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test-set constructions for the standard stuck-at fault model, as well as the usually intractable cell-fault model. We also give a practical test-set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional automatic test pattern generation.

Zero-aliasing space compaction of test responses using a single periodic output

A structure-independent method for space compaction in combinational circuits based on a new generic scheme is presented. It is shown that a single-output compactor can always be designed for compressing test responses of a circuit-under-test (CUT) with guaranteed zero-aliasing. Test responses from multiple outputs are compacted to a single periodic data stream. The compactor is independent of the fault model and can be designed only from the knowledge of the given test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT also detects all multiple stuck-at faults in the response logic and almost all faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design can be accomplished without any information about the structure and functionality of the CUT, it would be useful for testing embedded cores as their internal structures may not be transparent to the users.

On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits

Diagnosing multiple stuck-at faults in combinational circuits using singleand multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.

Self-repairable GALs

This paper describes the concept of self-testable and self-repairable Generic Array Logic (GAL) devices for high security and safety applications. A design methodology is proposed for self-repairing of a GAL which is a kind of Electrically Programmable Logic Devices (EPLDs). The fault-locating and fault-repairing architecture with electrically re-configurable GALs is presented. It uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair of all multiple stuck-at faults which might occur on E2CMOS cells in programmable AND plane. A self-repairing methodology is presented, based on our design architecture. A “column replacement” method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that a self-repairable GAL will last longer in the field. It gives also information on how many extra columns a GAL needs to reach a lifetime goal, in terms of simulation looping time, until the GAL is not useful any more. Therefore, an ideal point could be estimated, where the maximum reliability can be reached with the minimum cost.

Novel Test Generation Algorithm for Combination Circuits

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

NOVEL TEST GENERATION ALGORITHM FOR COMBINATION CIRCUITS

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

Isomorph-redundancy in sequential circuits

Design of irredundant and fully testable nonscan sequential circuits is a major concern of logic synthesis, as the presence of undetectable faults may render an ATPG intractable. This paper outlines some intriguing properties of isomorph faults, which are sequentially undetectable as well as redundant. An isomorph fault in a sequential circuit makes the state diagram of the faulty machine identical to that of the fault-free machine under certain renaming of states. Examples of reduced sequential machines whose circuit realization is combinationally irredundant, but isomorph-redundant, are hard to construct and very little is known about them. In this paper, many curious examples of such sequential circuits are presented wherein a single stuck-at fault causes isomorphic faulty machines. An infinite family of such circuits may, in fact, be constructed. It is shown that even two-level irredundant circuits obtained by synthesis tools may admit isomorph-redundancy under multiple stuck-at faults. Various classifications and related properties of isomorph faults are also reported. These results reveal new insight and understanding of redundancy in sequential circuits.

A New Method for Testing Re-Programmable PLAs

We present a method for obtaining a minimal set of test configurations and their associated set of test patterns that completely tests re-programmable Programmable Logic Arrays (PLAs) including EEPROM, UV-EPROM, and SRAM based re-programmable PLAs typically found in Complex Programmable Logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple stuck-at faults (including line and transistor faults) as well as all bridging faults in the PLA. Previously proposed test methods proposed for EEPROM based PLAs (IEEE Trans. on CAD, Vol. 13, No. 7, pp.935–939, 1994;Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1998, pp. 146–154) require additional test hardware as well as a large number of test configurations and vectors for complete testing. Our approach requires no modification to the PLA and only two or four test configurations, depending on the ratio of PLA product terms to inputs.

Novel test pattern generators for pseudoexhaustive testing

Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detectable multiple stuck-at faults in the circuit and all detectable combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information. They usually generate test sets that are several orders of magnitude larger than the minimum size pseudoexhaustive test set required for a specific circuit. In this paper, we describe hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minimum size test sets for the ISCAS benchmark circuits.

Universal delay test sets for logic networks

It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems.

Detecting exitory stuck-at faults in semimodular asynchronous circuits

Beerel (1994) showed that semimodular asynchronous circuits are totally self-checking with respect to multiple output stuck-at faults that are nonexitory and nonsubstitutional. We show that, in circuits with atomic gate implementations, it is possible to ensure that all exitory multiple output stuck-at faults will cause the circuit to halt.

Testability and test compaction for decision diagram circuits

Novel node realisations are used to represent reduced ordered binary, functional and Kronecker decision diagrams as irredundant combinational circuits. These types of decision diagrams are compact and able to represent very large switching functions. The resulting circuits are completely testable in the single and multiple stuck-at fault models. Theorems on diagnostic properties of these circuits are formulated. The high complexity of functions represented by decision diagram circuits calls for efficient test pattern generation and test set compaction tools. Such tools were implemented using a genetic algorithm which maximises the number of potential faults covered by every test pattern. Experimental results for decision diagrams with up to 1763 inputs and 5329 nodes are presented. The efficiency of the genetic algorithm in this application is estimated.

A diagnosis method for single logic design errors in gate‐level combinational circuits

This paper proposes a method for diagnosing logic design errors in gate-level combinational circuits, and discusses how to correct them. Some previously proposed design error models are explained at gate-level. This diagnosis method includes the vector pair analysis that has been developed for test pattern generation and fault diagnosis for multiple stuck-at faults. In vector pair analysis, logic values due to design errors are regarded as logic values caused by stuck-at faults and its results give some information on how to correct the design errors. However, since diagnosis using vector pair analysis cannot be applied to missing lines, their diagnosis uses another method based on the analysis of controlling values for input vectors with incorrect output responses. We also propose another diagnosis method for locating design errors in smaller areas, by the vector pair analysis. The experimental results for ISCAS'85 benchmark circuits show that the proposed method is effective for single design errors. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(6): 30–39, 1997

A diagnosis method for single logic design errors in gate-level combinational circuits

This paper proposes a method for diagnosing logic design errors in gate-level combinational circuits, and discusses how to correct them. Some previously proposed design error models are explained at gate-level. This diagnosis method includes the vector pair analysis that has been developed for test pattern generation and fault diagnosis for multiple stuck-at faults. In vector pair analysis, logic values due to design errors are regarded as logic values caused by stuck-at faults and its results give some information on how to correct the design errors. However, since diagnosis using vector pair analysis cannot be applied to missing lines, their diagnosis uses another method based on the analysis of controlling values for input vectors with incorrect output responses. We also propose another diagnosis method for locating design errors in smaller areas, by the vector pair analysis. The experimental results for ISCAS'85 benchmark circuits show that the proposed method is effective for single design errors.