Detection and identification of input/output stuck-at and bridging faults in combinational and sequential VLSI networks by universal tests

Abstract

In this paper we present universal tests for detection or identification of single and multiple stuck-at and bridging faults in combinational and sequential VLSI networks. Denote by P(T, F, m, k, s) the fraction of all devices with m inputs, k outputs and S feedback lines such that all faults from a set F of possible faults are detected (respectively, identified) by test T. We say that T is a universal test detecting (identifying) all faults from F if lim m → ∞ P(T, F, m, k, s) = 1. In this paper we consider single and multiple stuck-at and bridging faults at input or output lines. For these faults we construct corresponding universal tests T, estimate probabilities P(T, F, m, k, s) of fault detection or identification and present lower and upper bounds for the minimum number N(m, k, s) of test patterns in universal tests. Asymptotic optimality of the suggested universal tests is proved for the important case of single stuck-at and bridging faults. We also present practical examples of devices and tests which illustrate the usefulness of the estimates of minimum numbers N(m, k, s) of test patterns. For the universal tests T proposed in this paper probabilities P(T, F, m, k, s) of fault detection or identification converge to one very fast. This implies that these universal tests may be quite efficient either as a first step in a testing procedure or in the case when a broad spectrum of complex VLSI devices has to be tested.