Multiple Input Change Research Articles

Stochastic Hazard Analysis of Genetic Circuits in iBioSim and STAMINA.

In synthetic biology, combinational circuits are used to program cells for various new applications like biosensors, drug delivery systems, and biofuels. Similar to asynchronous electronic circuits, some combinational genetic circuits may show unwanted switching variations (glitches) caused by multiple input changes. Depending on the biological circuit, glitches can cause irreversible effects and jeopardize the circuit's functionality. This paper presents a stochastic analysis to predict glitch propensities for three implementations of a genetic circuit with known glitching behavior. The analysis uses STochastic Approximate Model-checker for INfinite-state Analysis (STAMINA), a tool for stochastic verification. The STAMINA results were validated by comparison to stochastic simulation in iBioSim resulting in further improvements of STAMINA. This paper demonstrates that stochastic verification can be utilized by genetic designers to evaluate design choices and input restrictions to achieve a desired reliability of operation.

Genetic Circuit Dynamics: Hazard and Glitch Analysis.

Multiple input changes can cause unwanted switching variations, or glitches, in the output of genetic combinational circuits. These glitches can have drastic effects if the output of the circuit causes irreversible changes within or with other cells such as a cascade of responses, apoptosis, or the release of a pharmaceutical in an off-target tissue. Therefore, avoiding unwanted variation of a circuit's output can be crucial for the safe operation of a genetic circuit. This paper investigates what causes unwanted switching variations in combinational genetic circuits using hazard analysis and a new dynamic model generator. The analysis is done in previously built and modeled genetic circuits with known glitching behavior. The dynamic models generated not only predict the same steady states as previous models but can also predict the unwanted switching variations that have been observed experimentally. Multiple input changes may cause glitches due to propagation delays within the circuit. Modifying the circuit's layout to alter these delays may change the likelihood of certain glitches, but it cannot eliminate the possibility that the glitch may occur. In other words, function hazards cannot be eliminated. Instead, they must be avoided by restricting the allowed input changes to the system. Logic hazards, on the other hand, can be avoided using hazard-free logic synthesis. This paper demonstrates this by showing how a circuit designed using a popular genetic design automation tool can be redesigned to eliminate logic hazards.

Test pattern generation using thermometer code counter in TPC technique for BIST implementation

This paper introduces a newly pattern generation with Test-Per-Clock technique for Built-In-Self-Test implementation. This proposed test vector generation generates Multiple Single Input Change vectors. Each pattern enforced in SIC vector as scan chain. To generate minimal transition sequence of test patterns, a scalable SIC counter and Thermometer Code Counter implemented. The proposed Multiple SIC vector generator is adaptable to both Test-Per-Scan, Test-Per-Clock techniques. This method developed a theory to evaluate MSIC scheme. Survey outcome demonstrates that, applying Multiple SIC test patterns on ISCAS C432 benchmark reduces the power consumption due to uniform distribution and lesser transition generated test patterns.

Low Cost Test Pattern Generation in Scan-Based BIST Schemes

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

Block-oriented feedforward control with demonstration to nonlinear parameterized Wiener modeling

Block-oriented modeling (BOM) is a multiple-input, multiple-output modeling approach for nonlinear dynamic processes. Current implementation of BOM into feedforward control (FFC) results in linearization of the model and decomposition into separate components for each input. This work presents a multiple-input BOM FFC approach that does not linearize and decompose the BOM into separate components for each input. This implementation uses a new FFC law that uses the complete BOM in the time domain. The approach is demonstrated with a Wiener model for a simulated continuous stirred tank reactor (CSTR) with four (4) measured inputs. The Wiener model is nonlinear in the physically-based dynamic parameters of the transfer functions and linear in the static parameters of the static gain function. The static gain function has a second order linear regression form with interaction and quadratic terms. The Wiener model is built under open-loop conditions using a Box–Behnken statistical experimental design consisting of 27 sequential step tests. Under a sequence of multiple input changes, the addition of this feedforward controller to the feedback controller reduced the standard deviation of the controlled variable from its set point by 70% in comparison to the response with only feedback control.

LOW POWER TEST PATTERN GENERATION FOR BIST APPLICATIONS

This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.

Implementation of MSIC-TPG in BIST Scheme

This paper introduces a test pattern generator (TPG) in order to use in built-in self-test(BIST). MSIC TPG generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. With the help of reconfigurable Johnson counter and a scalable SIC counter its easy to generate a class of minimum transition sequences. The proposed TPG is flexible to test-per-scan schemes. A theory is developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution, minimum transitions, and low input transition density. The Performances of the designed MSIC TPG and the circuit under test are evaluated. Simulation results shows that it can save delay time and power. It also achieves the target fault coverage without increasing the test length.

Temperature estimation for a plasma-propelled rocket engine [Applications of control

The VASIMR propulsion system is an ion propulsion system for spacecraft that uses magnetic fields to accelerate plasma to produce thrust. Undesired heat produced in the helicon section of VASIMR must be monitored and removed safely to avoid damage to system components, especially when higher power operating regimes are explored. This article demonstrates a strategy for distributed temperature estimation, based on OES measurement, and a model where the states represent the distributed temperature profile. OES provides a noninvasive measurement technique, which can be used as an output "correction" term for a state-estimation scheme. In this application, it is shown that the 2048 OES channels recorded can be accurately represented by only three principal components for temperature estimation. Use of the principal components as corrector terms in the state-space model dramatically improve model accuracy and the capability of the model to recover from unknown initial conditions and multiple system input changes.

Hardware Generation of Random Single Input Change Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under considerations the experimental results were based on a software generation of RSIC sequences that are easily generated. Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.

Automatic synthesis of extended burst-mode circuits. II. (Automatic synthesis)

We introduce a new design style called extended burst-mode. The extended burst-mode design style covers a wide spectrum of sequential circuits ranging from delay-insensitive to synchronous. We can synthesize multiple-input change asynchronous finite state machines and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize automatically using existing methods. Our implementation of extended burst-mode machines uses standard CMOS logic, generates low-latency outputs, and guarantees freedom from hazards at the gate level. In Part II, we present a complete set of automated sequential synthesis algorithms: hazard-free state assignment, hazard-free state minimization, and critical-rare-free state encoding. Experimental data from a large set of examples are presented and compared to competing methods whenever possible.

Automatic synthesis of extended burst-mode circuits. I. (Specification and hazard-free implementations)

We introduce a new design style called extended burst-mode. The extended burst-mode design style covers a wide spectrum of sequential circuits ranging from delay-insensitive to synchronous. We can synthesize multiple-input change asynchronous finite state machines and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize automatically using existing methods. Our implementation of extended burst-mode machines uses standard CMOS logic, generates low-latency outputs, and guarantees freedom from hazards at the gate level. In Part I, we formally define the extended burst-mode specification, provide an overview of the synthesis methods, and describe the hazard-free synthesis requirements for two different next-state logic synthesis methods: two-level sums-of-products implementation and generalized C-elements implementation. We also present an extension to existing theories for hazard-free combinational synthesis to handle nonmonotonic input changes.

Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams

We describe a new method for directly synthesizing a hazard-free multilevel logic implementation from a given logic specification. The method is based on free/ordered Binary Decision Diagrams (BDD's), and is naturally applicable to multiple-output logic functions. Given an incompletely-specified (multiple-output) Boolean function, the method produces a multilevel logic network that is hazard-free for a specified set of multiple-input changes. We assume an arbitrary (unbounded) gate and wire delay model under a pure delay (PD) assumption, we permit multiple-input changes, and we consider both static and dynamic hazards under the fundamental-mode assumption. Our framework is thus general and powerful. While it is not always possible to generate hazard-free implementations using our technique, we show that in some cases hazard-free multilevel implementations can be generated when hazard-free two-level representations cannot be found. This problem is generally regarded as a difficult problem and it has important applications in the field of asynchronous design. The method has been automated and applied to a number of examples. >

Exact two-level minimization of hazard-free logic with multiple-input changes

This paper describes a new method for exact hazard-free logic-minimization of Boolean functions. Given an incompletely-specified Boolean function, the method produces a minimum-cost sum-of-products implementation which is hazard-free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Quine-McCluskey algorithm. It has been automated and applied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard elimination is shown to be negligible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Synthesis of multiple input-change hazard-free combinational switching circuits without feedback†

This paper deals with hazards on outputs of combinational circuits without feedback for multiple input changes. A procedure is given to decompose a Boolean function into a feedback free circuit. The procedure either gives a logic hazard-free circuit or shows that the Boolean function cannot be broken down into a feedback free circuit which is free of logic hazards for multiple input changes. The procedure proves that all multiple input change combinational circuits cannot be implemented without dynamic logic hazards with no internal feedback. The result is therefore considerably different than the single input change and multiple input change static logic hazard cases.

Comments on "Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops"

Mealy synchronous machines cannot be implemented by Chuang and Das1 procedure for multiple-input change asynchronous circuits. The circuit must be changed to handle this common type of machine.

A logic hazard detection and elimination method

This paper is concerned with the detection and elimination of static logic hazards due to single and multiple input changes. The method involves only simple manipulation of the Boolean expression corresponding to the logic network. It not only detects the existence of hazards and determines the variable sets with respect to which the hazards exist, but also, for each of these sets, pin-points the subcubes within which each input transition involving exactly the changes of all variables in the set produces the hazardous output. Further, it can determine the terms the absence of which from the expression cause the hazards. Thus, the hazard can be eliminated by including these missing terms in the expression. The theoretical foundation of the method is given first followed by an example illustrating the procedure and its effectiveness. The procedure is formulated into two different algorithms, one for saving time and the other for saving memory. They have been implemented in FORTRAN. A related result on prime implicant generation is also included.

Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops

A synthesis method for multiple-input change asynchronous sequential machines is proposed. The method is based on the self-synchronization principle. The internal states are realized with edge-sensitive flip-flops which are triggered selectively. The new concept of selective triggering or controlled excitation results in considerable saving in logic and more flexible design. The state assignment is arbitrary, and the number of state variables required can be made absolutely minimum. A detailed comparison of the speed of operation is made with one of the well-known methods of realization. It is found that our realization is, in general, as fast, and sometimes could be even faster.

Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits

This paper deals with hazards on outputs of combinational switching circuits for multiple input changes. Certain types of function hazards are defined and are shown to be impossible to eliminate with any logic realization. Also, an interrelation between static and dynamic function hazards is established. Hazards due to delays in the logic are defined and a method of elimination is given for both the static and dynamic case.

Asynchronous Arbiters

When two or more processors attempt to simultaneously use a functional unit (memory, multiplier, etc.), an arbiter module must be employed to insure that processor requests are honored in sequence. The design of asynchronous arbiters is complicated because multiple input changes are allowed, and because inputs may change even if the circuit is not in a stable state. A practical arbiter and its implementation are presented. Implementation of various priority rules (linear, ring, mixed) is discussed, and building large arbiters with trees of two-user arbiters is considered.